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adc rf _ p , n program f lash 1 28 / 192 k b data ram 12 kb hf crystal osc lf crystal osc general purpose adc serial wire and jtag debug i nternal lf rc - osc g pio multiplexor switch chip manage r 1 . 8 v regulator bias 2 nd level interrupt controller rf _ tx _ alt _ p , n osca oscb pa [ 7 : 0 ] , pb [ 7 : 0 ] , pc [ 7 : 0 ] encryption acclerator if always powered domain arm ? cortex tm - m 3 cpu with nvic and mpu vreg _ out watchdog pa select lna pa pa dac mac + baseband sleep timer por nreset general purpose timers gpio registers uart / spi / twi synth i nternal hf rc - osc tx _ active swclk , jtck calibration adc packet trace cpu debug tpiu / itm / fpb / dwt 1 . 25 v regulator vdd _ core adc rf _ p, n program f lash 128 /192 k b data ram 12 kb hf crystal osc lf crystal osc general purpose adc serial wire and jtag debug i nternal lf rc - osc g pio multiplexor switch chip manage r 1 .8v regulator bias 2 nd level interrupt controller rf _ tx _ alt _ p , n osca oscb pa[ 7 : 0 ] , pb[ 7 : 0 ] , pc [ 7 : 0 ] encryption acclerator if always powered domain arm ? cortex tm - m 3 cpu with nvic and mpu vreg _ out watchdog pa select lna pa pa dac mac + baseband sleep timer por nreset general purpose timers gpio registers uart / spi / twi synth i nternal hf rc - osc tx _ active swclk , jtck calibration adc packet trace cpu debug tpiu / itm / fpb / dwt 1. 25v regulator vdd _ core EM351 / em357 high - performance, integrated zigbee/802.15.4 system -on- chip ? complete system - on - chip ? 32- bit arm ? cortex ? - m3 processor ? 2.4 ghz ieee 802.15.4 - 2003 transceiver & lower mac ? 128 or 192 kb f lash , with optional read protection ? 12 kb ram memory ? aes128 encryption accelerator ? fl exible adc, uart/ spi/ twi serial communications, and general purpose timers ? 24 highly configurable gpio s with schmitt trigger inputs ? indust r y - leading arm ? cortex ? - m3 processor ? leading 32 - bit processing performance ? highly efficient thumb - 2 instruction set ? operation at 6, 12 , or 24 mhz ? flexible nested vectored interrupt controller ? low power consumption, advanced management ? rx current (w/ cpu): 2 6 ma ? tx current (w/ cpu, +3 dbm tx): 31 ma ? low deep sleep current, with retained ram and gpio : 400 na with out /800 na with sleep timer ? low - frequency internal rc oscillator for low - power sleep timing ? high - frequency internal rc oscillator for fast ( 110 sec) processor start - up from sleep ? exceptional rf performance ? normal mode l ink b udget u p to 103 db; configurable up to 1 10 db ? - 100 dbm normal rx sensitivity; configu r able to - 10 2 dbm (1% per, 20 byte packet) ? +3 db normal mode output power; configurable up to + 8 dbm ? robust wi - fi and bluetooth coexistence ? innovative network and processor debug ? packet trace port for non - intrusive packet trace with ember development tools ? serial wire /jtag interface ? standard arm debug capabilities: flash patch & breakpoint ; data watchpoint & trace ; instrumentation trace macro cell ? application flexibility ? single voltage operation: 2.1 - 3.6 v with internal 1.8 v and 1.25 v regulators ? optional 32.768 khz crystal for higher timer accuracy ? low external component count with si n gle 24 mh z crystal ? support for external power amplifier ? small 7x7 mm 48 - pin qfn package silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel : 1 +( 512) 416- 8500 fax: 1 +( 512) 416- 9669 to ll free: 1 +( 877) 444- 3032 www.silabs.com 120- 035x - 000 rev. 1.2 final
EM351 / em357 general description the em35 1 and em357 are fully integrated system - on - chip s that integrate a 2.4 ghz, ieee 802.15.4 - 2003 - compliant transceiver, 32- bit arm ? cortex ? - m3 microprocessor , f lash and ram memory , and peripherals of use to designers of zigbee - based systems . the transceiver us es an efficient architecture that exceeds the dynamic range requirements imposed by the ieee 802.15.4 - 2003 standard by over 15 db. the integrated receive channel filtering allows for robust co - existence with other communication standards in the 2.4 ghz spectrum , such as ieee 802.11 - 2007 and bluetooth. the integrated regulator, vco, loop filter, and power amplifier keep th e external component count low. an optional high performance radio mode ( boost mode) is software - selectable to boost dynamic range . the integrated 32 - bit arm ? cortex ? - m3 microprocessor is highly optimized for high performance, low power consumption, and ef ficient memory utilization . including an integrated mpu, it supports two different modes of operation ? privileged m ode and user m ode . this architecture could allow for separation of the networking stack from the application code , and prevents unwanted modif ication of restricted areas of memory and registers resulting in increased stability and reliability of deployed solutions. the em35 1 has 128 kb of e mbedded f lash memory and the em357 has 192 kb of embedded flash memory. both chips have 12 kb of integrated ram for data and program storage. the ember s oftware for the em35x employs an effective wear - leveling algorithm that optimize s t he lifetime of the e mbedded f lash. to maintain the strict timing requirements imposed by the zigbee and ieee 802.15.4 - 2003 standard s , the em35 x integrates a number of mac functions , aes128 encryption accelerator, and automatic crc handling into the hardware. the mac hardware handles automatic ack transmission and reception, automatic backoff delay, and clear channel assessment for transmission, as well as automatic filtering of received packets. the ember packet trace interface is also integrated with the mac, allowing complete, non - intrusive capture of all packets to and from the em35 x with ember d evelopment tools. the em35 x offers a number of advanced power management features that enable long battery life. a high - frequency internal rc oscillator allows the processor core to begin code execution quickly upon waking . various deep sleep modes are available with less than 1 a p ower consumption while retaining ram contents. to support user - defined applications , on - chip peripherals include uart, spi, twi , adc , and general - purpose timers , as well as up to 24 gpios . additionally , an integrated voltage regulator, power - on - reset circuit, and sleep timer are available. finally, the em35 x utilizes standard serial wire and jtag interfaces for powerful softwa re debug ging and programming of the arm cortex ? - m3 core . the em35 x integrates the standard arm system debug components: flash patch and breakpoint ( fpb ), data watchpoint and trace (dwt), and instrumentation trace macroce l l ( itm ). target applications for the em35 x include the following : ? smart energy ? building automation and control ? home automation and control ? security and monitoring ? general zigbee wireless sensor networking this technical data sheet details the em35 x features available to cus tomers using it with ember software . final 120 - 035x - 000 rev. 1.2
EM351 / em357 contents 1 pin assignments 1 - 1 2 electrical characteristics 2 - 1 2.1 absolute maximum ratings 2 - 1 2.2 recommended operating conditions 2 - 1 2.3 environmental characteristics 2 - 2 2.4 dc electrical characteristics 2 - 2 2.5 digital i/o specifications 2 - 6 2.6 non - rf system electrical characteristics 2 - 8 2.7 rf electrical characteristics 2 - 8 2.7.1 receive 2 - 8 2 .7.2 transmit 2 - 10 2.7.3 synthesizer 2 - 12 3 top - level functional description 3 - 1 4 radio module 4 - 1 4.1 receive (rx) path 4 - 1 4.1.1 rx baseband 4 - 1 4.1.2 rssi and cca 4 - 1 4.2 transmit (tx) path 4 - 1 4.2.1 tx baseband 4 - 1 4.2.2 tx_active and ntx_active signals 4 - 1 4.3 calibration 4 - 2 4.4 integrated mac module 4 - 2 4.5 packet trace interface (pti) 4 - 2 4.6 random number generator 4 - 2 5 arm ? cortex ? - m3 and memory modules 5 - 1 5.1 arm ? cortex? - m3 microprocessor 5 - 1 5.2 embedded memory 5 - 2 5.2.1 flash memory 5 - 4 5.2.2 ram 5 - 7 5.2.3 registers 5 - 8 5.3 memory protection unit 5 - 8 6 system modules 6 - 1 6.1 power domains 6 - 2 6.1.1 internally regulated power 6 - 2 6.1.2 externally regulated power 6 - 2 6.2 resets 6 - 3 6.2.1 reset sources 6 - 3 6.2.2 reset recording 6 - 5 6.2.3 reset generation module 6 - 5 6.3 clocks 6 - 6 6.3.1 high - frequency internal rc oscillator (oschf) 6 - 8 6.3.2 high - frequency crystal oscillator (osc24m) 6 - 8 6.3.3 low - frequency internal rc oscillator (oscrc) 6 - 9 6.3.4 low - frequency crystal oscillator (os c32k) 6 - 9 6.3.5 clock switching 6 - 10 6.4 system timers 6 - 11 6.4.1 watchdog timer 6 - 11 6.4.2 sleep timer 6 - 11 6.4.3 event timer 6 - 11 6.5 power management 6 - 11 6.5.1 wake sources 6 - 12 6.5.2 basic sleep modes 6 - 13 6.5.3 further options for deep sleep 6 - 14 6.5.4 use of debugger with sleep modes 6 - 14 6.5.5 registers 6 - 15 6.6 security accelerator 6 - 15 7 gpio (general purpose input / output) 7 - 1 7.1 gpio ports 7 - 1 7.2 configuration 7 - 2 7.3 forced functions 7 - 3 7.4 reset 7 - 4 7.5 boot configuration 7 - 4 7.6 gpio modes 7 - 5 7.6.1 analog mode 7 - 5 7.6.2 input mode 7 - 5 7.6.3 output mode 7 - 6 7.6.4 alternate output mode 7 - 6 7.7 wake monitoring 7 - 6 7.8 external interrupts 7 - 7 7.9 debug control and status 7 - 8 7.10 gpio signal assignment summary 7 - 8 7.11 registers 7 - 10 8 serial controllers 8 - 1 8.1 overview 8 - 1 8.2 configuration 8 - 2 8.2.1 registers 8 - 3 8.3 spi - master mode 8 - 6 8.3.1 gpio usage 8 - 6 final 120 - 035x - 000 rev. 1.2
EM351 / em357 8.3.2 set up and configuration 8 - 7 8.3.3 operation 8 - 8 8.3.4 interrupts 8 - 9 8.3.5 registers 8 - 10 8.4 spi - slave mode 8 - 14 8.4.1 gpio usage 8 - 14 8.4.2 set up and configuration 8 - 15 8.4.3 operation 8 - 16 8.4.4 dma 8 - 17 8.4.5 interrupts 8 - 17 8.4.6 registers 8 - 18 8.5 twi - two wire serial interfaces 8 - 18 8.5.1 gpio usage 8 - 18 8.5.2 set up and configuration 8 - 18 8.5.3 constructing frames 8 - 19 8.5.4 interrupts 8 - 21 8.5.5 registers 8 - 22 8.6 uart - universal asynchronous receiver / transmitter 8 - 24 8.6.1 gpio usage 8 - 24 8.6.2 set up and configuration 8 - 25 8.6.3 fifos 8 - 27 8.6.4 rts/cts flow control 8 - 27 8.6.5 dma 8 - 28 8.6.6 interrupts 8 - 28 8.6.7 registers 8 - 29 8.7 dma channels 8 - 32 8.7.1 registers 8 - 34 9 general purpose timers (tim1 and tim2) 9 - 1 9.1 introduction 9 - 1 9.2 gpio usage 9 - 3 9.3 timer functional description 9 - 3 9.3.1 time - base unit 9 - 3 9.3.2 counter modes 9 - 4 9.3.3 clock selection 9 - 9 9.3.4 capture/compare channels 9 - 12 9.3.5 input capture mode 9 - 13 9.3.6 pwm input mode 9 - 14 9.3.7 forced output mode 9 - 15 9.3.8 output compare mode 9 - 15 9.3.9 pwm mode 9 - 16 9.3.10 one - pulse mode 9 - 19 9.3.11 encoder interface mode 9 - 20 9.3.12 timer input xor function 9 - 22 9.3.13 timers and external trigger synchronization 9 - 22 9.3.14 timer synchronization 9 - 25 9.3.15 timer signal descriptions 9 - 29 9.4 interrupts 9 - 30 9.5 registers 9 - 31 10 adc (analog to digital converter) 10- 1 10.1 setup and configuration 10- 1 10.1.1 gpio usage 10- 2 10.1.2 voltage reference 10- 2 10.1.3 offset/gain correction 10- 2 10.1.4 dma 10- 3 10.1.5 adc configuration register 10- 3 10.2 interrupts 10- 5 10.3 operation 10- 6 10.4 calibration 10- 7 10.5 adc key parameters 10- 8 10.6 registers 10- 13 11 interrupt system 11- 1 11.1 nested vectored interrupt controller (nvic) 11- 1 11.2 event manager 11- 3 11.3 non - maskable interrupt (nmi) 11- 6 11.4 faults 11- 6 11.5 registers 11- 7 12 trace port interface unit (tpiu) 12- 1 13 instrumentation trace macrocell (itm) 13- 1 14 data watchpoint and trace (dwt) 14- 1 15 flash patch and breakpoint (fpb) 15- 1 16 integrated voltage regulator 16- 1 17 serial wire and jtag (swj) interface 17- 1 18 typical application 18- 1 19 mechanical details 19- 1 19.1 qfn48 footprint recommendations 19- 1 19.2 solder temperature profile 19- 3 20 part marking 20- 1 21 ordering information 21- 1 22 shipping box label 22- 1 23 revision history 23- 1 appendix a register address table a - 1 appendix b abbreviations and acronyms b- 1 appendix c references c - 1 final 120 - 035x - 000 rev. 1.2
EM351 / em357 1 pin assignment s figure 1 - 1 . em35x pin assignments vdd _ 24 mh z vdd _ vco rf _ n rf _ p vdd _ rf rf _ tx _ alt _ p rf _ tx _ alt _ n vdd _ if nc vdd _ padsa pc 5 , tx _ active pb 0 , vref , i rq a , traceclk , tim 1 clk , t i m 2 msk pc 4 , jtms , swdio pc 3 , jtdi pc 2 , jtdo , swo swclk , jtck pb 2 , sc 1 miso , sc 1 mosi , sc 1 scl , sc 1 rxd , t im 2 c 2 pb 1 , sc 1 mis o , sc 1 mosi , sc 1 sda , sc 1 txd , t im 2 c 1 pa 6 , t i m 1 c 3 vdd _ pads pa 5 , adc 5 , p ti _ data , nbootmode , tracedata 3 pa 4 , adc 4 , p ti _ en , tracedata 2 pa 3 , sc 2 n ssel , traceclk , t im 2 c 2 vdd _ pads pc 1 , adc 3 , swo , tracedata 0 vdd _ mem pc 0 , jrst , i rq d , tracedata 1 pb 7 , adc 2 , i rq c , tm 1 c 2 pb 6 , adc 1 , i rq b , t i m 1 c 1 pb 5 , adc 0 , tim 2 clk , t i m 1 msk vdd _ core vdd _ pre vdd _ synth oscb osca pa 2 , t im 2 c 4 , sc 2 scl , sc 2 sclk vdd _ pads pa 1 , t im 2 c 3 , sc 2 sda , sc 2 miso pb 4 , t im 2 c 4 , sc 1 n rts , sc 1 n ssel pb 3 , tim 2 c 3 , sc 1 n cts , sc 1 sclk vdd _ core vdd _ pads vreg _ out pc 6 , osc 32 b , ntx _ active pa 0 , t im 2 c 1 , sc 2 mosi pc 7 , osc 32 a , osc 32 _ ext pa 7 , tim 1 c 4 , reg _ en 13 14 15 16 17 18 19 20 21 22 23 24 12 11 nreset 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 48 47 46 45 44 43 42 41 40 39 38 37 49 gnd em 3 5 x refer to chapter 7, gpio fo r details about selecting gpio pin functions. 1 -1 120 - 035x - 000 rev. 1.2 final
EM351 / em357 table 1 - 1 . em35x pin descriptions pin # signal direction description 1 vdd_24mhz power 1.8 v h igh - f requency o scillator s upply 2 vdd_vco power 1.8 v vco s upply 3 rf_p i /o differential (with rf_n ) r eceiver i nput/ t ransmitter o utput 4 rf_n i /o differen tial (with rf_p ) r eceiver i nput/ t ransmitter o utput 5 vdd_rf power 1.8 v rf supply (lna and pa) 6 rf_ tx_alt _p o differential (with rf_tx_alt_ n ) transmitter output (optional) 7 rf_ tx_alt _n o differential (with rf_tx_alt_ p ) transmitter output (optional) 8 vdd_if power 1.8 v if supply (mixers and filters) 9 nc do not connect 10 vdd_padsa power analog pad supply (1.8 v) 11 pc5 i/o digital i/o tx_active o logic - level control for external r x /t x switch. the em35 x baseband controls tx_active and drives it high (vdd_pads) when in t x mode. select alternate output function with gpio_pccfgh[7:4] 12 nreset i active low chip reset (internal pull - up) 13 pc6 i/o digital i/o osc32b i/o 32.768 khz crystal oscillator select analog function with gpio_pccfgh[11:8] ntx_active o inverted tx_active signal (see pc5 ) select alternate output function with gpio_pccfgh[11:8] 14 pc7 i/o digital i/o osc32a i/o 32.768 khz crystal oscillator select analog function with gpio_pccfgh[15:12] osc32_ext i digital 32 .768 khz clock input source 15 vreg_out power regulator output (1.8 v while awake , 0 v during deep sleep) 16 vdd_pads power pads supply (2.1 - 3.6 v) 17 vdd_core power 1.2 5 v digital core supply decoupling 18 pa7 i/o high current digital i/o disable reg_en with gpio_dbgcfg[4 ] tim1c4 o timer 1 channel 4 output enable timer output with tim1_ccer select alternate output function with gpio_pacfgh[15:12 ] disable reg_en with gpio_dbgcfg[4] tim1c4 i timer 1 channel 4 input cannot be remapped reg_en o external regulator open drain output enabled after reset 19 pb3 i/o digital i/o 1 -2 120 - 035x - 000 rev. 1.2 final
EM351 / em357 pin # signal direction description tim2c3 (see also pin 22) o timer 2 channel 3 output enable remap with tim2_or[6] enable timer output in tim2_ccer select alternate output function with gpio_pbcfgl[15:12] tim2c3 (see also pin 22) i timer 2 channel 3 input enable remap with tim2_or[6] sc1ncts i uart cts handshake of serial controller 1 enable with sc1_uartc fg[5] select uart with sc1_mode sc1s clk o spi master clock of serial controller 1 either disable timer output in tim2_ccer, or disable remap with tim2_or[6] enable master with sc1_spicfg[4] select spi with sc1_mode select alternate output function with gpio_p bcfgl[15:12 ] sc1s clk i spi slave clock of serial controller 1 enable slave with sc1_spicfg[4] select spi with sc1_mode 20 pb4 i/o digital i/o tim2c4 (see also pin 24) o timer 2 channel 4 output enable remap with tim2_or[7] enable timer output in tim2_ccer select alternate output function with gpio_pbcfgh[3:0] tim2c4 (see also pin 24) i timer 2 channel 4 input enable remap with tim2_or[7] sc1n rts o uart rts handshake of serial controller 1 either disable timer output in tim2_ccer, or disable remap with tim2_or[7] enable with sc1_uartc fg[5] select uart with sc1_mode select alternate output function with gpio_pbcfgh[3:0] sc1nssel i spi slave select of serial controller 1 enable slave with sc1_spicfg[4] select spi with sc1_mode 21 pa0 i/o digital i/o tim2c1 (see also pin 30) o timer 2 channel 1 output disable remap with tim2_or[4] enable timer output in tim2_ccer select alternate output function with gpio_pacfgl[3:0] tim2c1 (see also pin 30) i timer 2 channel 1 input disable remap with tim2_or[4] 1 -3 120 - 035x - 000 rev. 1.2 final
EM351 / em357 pin # signal direction description sc2 mosi o spi master data out of serial controller 2 either disable timer output in tim2_ccer, or enable remap with tim2_or[4] enable master with sc2_spicfg[4] select spi with sc2_mode select alternate output function with gpio_pacfgl[3:0] sc2 mosi i spi slave data in of serial controller 2 enable slave with sc2_spicfg[4 ] select spi with sc2_mode 22 pa1 i/o digital i/o tim2c3 (see also pin 19) o timer 2 channel 3 output disable remap with tim2_or[6] enable timer output in tim2_ccer select alternate output function with gpio_pacfgl[7:4] tim2c3 (see also pin 19) i timer 2 channel 3 input disable remap with tim2_or[6] sc2 sda i/o twi data of serial controller 2 either disable timer output in tim2_ccer, or enable remap with tim2_or[6] select twi with sc2_mode select alternate open - drain output function with gpio_pacfgl[7:4] sc2 miso o spi slave data out of serial controller 2 either disable timer output in tim2_ccer, or enable remap with tim2_or[6] enable slave with sc2_spicfg[4] select spi with sc2_mode select alternate output function with gpio_pacfgl[7:4] sc2 miso i spi master data in of serial controller 2 enable slave with sc2_spicfg[4] select spi with sc2_mode 23 vdd_pads power pads supply (2.1 - 3.6 v) 24 pa2 i/o digital i/o tim2c4 (see also pin 20) o timer 2 channel 4 output disable remap with tim2_or[7] enable timer output in tim2_ccer select alternate output function with gpio_pacfgl[11:8] tim2c4 (see also pin 20) i timer 2 channel 4 input disable remap with tim2_or[7] sc2 scl i/o twi clock of serial controller 2 either disable timer output in tim2_ccer, or enable remap with tim2_or[7] select twi with sc2_mode select alternate open - drain output function with gpio_pacfgl[11:8] 1 -4 120 - 035x - 000 rev. 1.2 final
EM351 / em357 pin # signal direction description sc2 sclk o spi master clock of serial controller 2 either disable timer output in tim2_ccer, or enable remap with tim2_or[7] enable master with sc2_spicfg[4] select spi with sc2_mode select alternate output function with gpio_pacfgl[11: 8] sc2 sclk i spi slave clock of serial controller 2 enable slave with sc2_spicfg[4] select spi with sc2_mode 25 pa3 i/o digital i/o sc2nssel i spi slave select of serial controller 2 enable slave with sc2_spicfg[4] select spi with sc2_mode traceclk (see also pin 36) o synchronous cpu trace clock either disable timer output in tim2_ccer , or enable remap with tim2_or[5] enable trace interface in arm core select alternate output function with gpio_pacfgl[15:12] tim2c2 (see also pin 31) o timer 2 channel 2 output disable remap with tim2_or[5] enable timer output in tim2_ccer select alternate output function with gpio_pacfgl[15:12] tim2c2 (see also pin 31) i timer 2 channel 2 input disable remap with tim2_or[5] 26 pa4 i/o digital i/o adc4 analog adc input 4 select analog function with gpio_pacfgh[3:0] p ti _en o frame signal of packet trace interface (pti) disable trace interface in arm core enable pti in ember software select alternate output function with gpio_pacfgh[3:0] tracedata2 o synchronous cpu trace data bit 2 select 4 - wire synchronous trace interface in arm core enable trace interface in arm core select alternate output function with gpio_pacfgh[3:0] 27 pa5 i/o digital i/o adc5 analog adc input 5 select analog function with gpio_pacfgh[7:4] p ti _data o data signal of packet trace interface (pti) disable trace interface in arm core enable pti in ember software select alternate output function with gpio_pacfgh[7:4] nbootmode i activate fib monitor instead of main program or bootloader when coming out of reset . signal is active during and immediately after a reset on nreset. see section 7.5, boot configuration, in chapter 7, gpio. 1 -5 120 - 035x - 000 rev. 1.2 final
EM351 / em357 pin # signal direction description tracedata3 o synchronous cpu trace data bit 3 select 4 - wire synchronous trace interface in arm core enable trace interface in arm core select alternate output function with gpio_pacfgh[7:4] 28 vdd_pads power pads supply (2.1 - 3.6 v) 29 pa6 i/o high current digital i/o tim1c3 o timer 1 channel 3 output enable timer output in tim1_ccer select alternate output function with gpio_pacfgh[11:8] tim1c3 i timer 1 channel 3 input cannot be remapped 30 pb1 i/o digital i/o sc1miso o spi slave data out of serial controller 1 either disable timer output in tim2_ccer, or disable remap with tim2_or[4] select spi with sc1_mode select slave with sc1_spicr select alternate output function with gpio_pbcfgl[7:4] sc1 mo si o spi master data out of serial controller 1 either disable timer output in tim2_ccer, or disable remap with tim2_or[4] select spi with sc1_mode select master with sc1_spicr select alternate output function with gpio_pbcfgl[7:4] sc1 sda i/o twi data of serial controller 1 either disable timer output in tim2_ccer, or disable remap with tim2_or[4] select twi with sc1_mode select alternate open - drain output function with gpio_pbcfgl[7:4] sc1 txd o uart transmit data of serial controller 1 either disable timer output in tim2_ccer, or disable remap with tim2_or[4] select uart with sc1_mode select alternate output function wi th gpio_pbcfgl[7:4] tim2c1 (see also pin 21) o timer 2 channel 1 output enable remap with tim2_or[4] enable timer output in tim2_ccer select alternate output function with gpio_pacfgl[ 7:4 ] tim2c1 (see also pin 21) i timer 2 channel 1 input disable remap with tim2_or[4] 31 pb2 i/o digital i/o sc1 mi so i spi master data in of serial controller 1 select spi with sc1_mode select master with sc1_spicr 1 -6 120 - 035x - 000 rev. 1.2 final
EM351 / em357 pin # signal direction description sc1mosi i spi slave data in of serial controller 1 select spi with sc1_mode select slave with sc1_spicr sc1 scl i/o twi clock of serial controller 1 either disable timer output in tim2_ccer, or disable remap with tim2_or[5] select twi with sc1_mode select alternate open - drain output function with gpio_pbcfgl[11:8] sc1 rxd i uart receive data of serial controller 1 select uart with sc1_mode tim2c2 (see also pin 25) o timer 2 channel 2 output enable remap with tim2_or[5] enable timer output in tim2_ccer select alternate output function with gpio_pbcfgl[11:8] tim2c2 (see also pin 25) i timer 2 channel 2 input enable remap with tim2_or[5] 32 swclk i/o serial wire clock input/output with debugger selected when in serial wire mode (see jtms description , pin 35 ) jtck i jtag clock input from debugger selected when in jtag mode (default mode, see jtms description , pin 35 ) internal pull - down is enabled 33 pc2 i/o digital i/o enable with gpio_dbgcfg[5] jtdo o jtag data out to debugger selected when in jtag mode (default mode, see jtms description , pin 35 ) swo o serial wire output asynchronous trace output to debugger select asynchronous trace interface in arm core enable trace interface in arm core select alternate output function with gpio_pccfgl[11:8] enable serial wire mode (see jtms description , pin 35 ) internal pull - up is enabled 34 pc3 i/o digital i/o either enable with gpio_dbgcfg[5], or enable serial wire mode (see jtms description) jtdi i jtag data in from debugger selected when in jtag mode (default mode, see jtms description , pin 35 ) internal pull - up is enabled 35 pc4 i/o digital i/o enable with gpio_dbgcfg[5] 1 -7 120 - 035x - 000 rev. 1.2 final
EM351 / em357 pin # signal direction description jtms i jtag mode select from debugger selected when in jtag mode (default mode) jtag mode is enabled after po wer - up or by forcing nreset low select serial wire mode using the arm - defined protocol through a debugger internal pull - up is enabled swdio i/o serial w ire bidirectional data to/from debugger enable serial wire mode (see jtms description) select serial wire mode using the arm - defined protocol through a debugger internal pull - up is enabled 36 pb0 i/o digital i/o vref analog o adc reference output enable analog function with gpio_pbcfgl[3:0] vref analog i adc reference input enable analog function with gpio_pbcfgl[3:0] enable reference output with a n ember system function irqa i external interrupt source a traceclk (see also pin 25) o synchronous cpu trace clock enable trace interface in arm core select alternate output function with gpio_pbcfgl[3:0] tim1clk i timer 1 external clock input tim2msk i timer 2 external clock mask input 37 vdd_pads power pads supply (2.1 - 3.6 v) 38 pc1 i/o digital i/o adc3 analog adc input 3 enable analog function with gpio_pccfgl[7:4] swo (see also pin 33) o serial wire output asynchronous trace output to debugger select asynchronous trace interface in arm core enable trace interface in arm core select alternate output function with gpio_pccfgl[7:4] tracedata0 o synchronous cpu trace data bit 0 select 1 - , 2 - or 4 - wire synchronous trace interface in arm core enable trace interface in arm core select alternate output function with gpio_pccfgl[ 7:4 ] 39 vdd_mem power 1.8 v supply (flash , ram) 40 pc0 i/o high current digital i/o either enable with gpio_dbgcfg[5] , or enable serial wire mode (see jtms description, pin 35 ) and disable tracedata1 jrst i jtag reset input from debugger selected when in jtag mode (default mode, see jtms description) and tracedata1 is disabled internal pull - up is enabled irqd 1 i default external interrupt source d 1 -8 120 - 035x - 000 rev. 1.2 final
EM351 / em357 pin # signal direction description tracedata1 o synchronous cpu trace data bit 1 select 2 - or 4 - wire synchronous trace interface in arm core enable trace interface in arm core select alternate output function with gpio_pccfgl[3:0] 41 pb7 i/o high current digital i/o adc2 analog adc input 2 enable analog function with gpio_pbcfgh[15:12] irqc 1 i default external interrupt source c tim1c2 o timer 1 channel 2 output enable timer output in tim1_ccer select alternate output function with gpio_pbcfgh[15:12] tim1c2 i timer 1 channel 2 input cannot be remapped 42 pb6 i/o high current digital i/o adc1 analog adc input 1 enable analog function with gpio_pbcfgh[11:8] irqb i external interrupt source b tim1c1 o timer 1 channel 1 output enable timer output in tim1_ccer select alternate output function with gpio_pbcfgh[11:8] tim1c1 i timer 1 channel 1 input cannot be remapped 43 pb5 i/o digital i/o adc0 analog adc input 0 enable analog function with gpio_pbcfgh[7:4] tim2clk i timer 2 external clock input tim1msk i timer 1 external clock mask input 44 vdd_core power 1.25 v digital core supply decoupling 45 vdd_pre power 1.8 v p rescaler s upply 46 vdd_synth power 1 .8 v s ynthesizer s upply 47 oscb i/o 24 mhz crystal oscillator or left open when using external clock input on osca 48 osca i/o 24 mhz crystal oscillator or external clock input . ( an external clock input should only be used for test and debug purposes . if used in this manner, the external clock input should be a 1.8 v, 50% duty cycle, square wave. ) 49 gnd ground ground supply pad in the bottom center of the package forms pin 49 . s ee the various silicon labs em3 5 x reference design documentation for pcb considerations . 1 irqc and irqd external interrupts can be mapped to any digital i/o pin using the gpio_irqsel and gpio_irqdsel registers. 1 -9 120 - 035x - 000 rev. 1.2 final
EM351 / em357 2 electrical characteristics 2.1 absolute maximum ratings table 2 - 1 lists the absolute maximum ratings for the em3 5 x . table 2 - 1 . absolute maximum ratings parameter test conditions min. max. unit regulator input voltage (vdd_pads) - 0.3 + 3.6 v analog, memory and core voltage (vdd_24mhz, vdd_vco, vdd_rf, vdd_if, vdd_padsa, vdd_ mem , vdd_pre, vdd_synth, vdd_core) - 0.3 + 2.0 v voltage on rf_p,n; rf_tx_alt_p,n - 0.3 + 3.6 v rf input power ( for max level for correct packet reception see table 2 - 7 ) rx signal into a lossless balun +15 dbm voltage on any gpio (pa[7:0], pb[7:0], pc[7:0]) , swclk , nreset, vreg_out - 0.3 vdd_pads +0.3 v voltage on any gpio pin (pa4, pa5, pb5, pb6, pb7, pc1), when used as an input to the general purpose adc - 0.3 2.0 v voltage on osca, oscb , nc - 0.3 vdd_padsa +0.3 v storage temperature - 40 +140 c 2.2 recommended operating conditions table 2 - 2 lists the rated operating conditions of the em35x. table 2 - 2 . operating cond itions parameter test conditions min. typ. max. unit regulator input voltage (vdd_pads) 2.1 3.6 v analog and memory input voltage (vdd_24mhz, vdd_vco, vdd_rf, vdd_if, vdd_padsa, vdd_ mem, vdd_pre, vdd_synth) 1.7 1.8 1.9 v core input voltage when supplied from internal regulator (vdd_core) 1.18 1.25 1.32 v core input voltage when supplied externally (vdd_core) 1.18 1.9 v operating t emperature range - 40 +85 c 2 -1 120 - 035x - 000 rev. 1.2 final
EM351 / em357 2.3 environmental characteristics table 2 - 3 lists the rated environmental characteristics of the em35x. table 2 - 3 . environmental characteristics parameter test conditions min. typ. max. unit esd (human body model) on any p in 2 kv esd (charged device model) non - rf p ins 400 v esd (charged device model) rf p ins 225 v moisture sensitivity level (msl) msl 2 2.4 dc electrical characteristics table 2 - 4 lists the dc electrical characteristics of the em35x. table 2 - 4 . dc characteristics parameter test conditions min. typ. max. unit regulator input voltage (vdd_pads) 2.1 3.6 v power supply range (vdd_mem ) regulator output or external input 1.7 1.8 1.9 v power supply range (vdd_core) regulator output 1.18 1.25 1.32 v deep sleep current quiescent current, internal rc oscillator disabled - 40c, vdd_pads=3.6 v 0.4 a + 25 c, vdd_pads=3.6 v 0.4 a +85 c, vdd_pads=3.6 v 0.7 a quiescent current, including internal rc oscillator - 40c, vdd_pads=3.6 v 0.7 a + 25 c, vdd_pads=3.6 v 0.7 a +85 c, vdd_pads=3.6 v 1.1 a quiescent current, including 32.768 khz oscillator - 40c, vdd_pads=3.6 v 0.8 a + 25 c, vdd_pads=3.6 v 1.0 a +85 c, vdd_pads=3.6 v 1.5 a quiescent current, including internal rc oscillator and 32.768 khz oscillator - 40c, vdd_pads=3.6 v 1.1 a + 25 c, vdd_pads=3.6 v 1. 3 a +85 c, vdd_pads=3.6 v 1.8 a simulated deep sleep (debug mode) current with no debugger activity 300 a 2 -2 120 - 035x - 000 rev. 1.2 final
EM351 / em357 parameter test conditions min. typ. max. unit reset current quiescent current, nreset asserted typ at 25 c /3 .0 v max at 85 c /3.6 v 1.2 2.0 ma processor and p eripheral c urrents arm ? cortex tm - m3 , ram, and f lash memory 25c, 1.8 v memory and 1.25 v core arm ? cortex tm - m3 running at 12 mhz from crystal oscillator radio and all peripherals off 6.5 ma arm ? cortex tm - m3, ram, and f lash memory 25c, 1.8 v memory and 1.25 v core arm ? cortex tm - m3 running at 24 mhz from crystal oscillator radio and all peripherals off 7.5 ma arm ? cortex tm - m3, ram, and f lash memory sleep current 25c, 1.8 v memory and 1.25 v core arm ? cortex tm - m3 sleeping, cpu clock set to 12 mhz from the crystal oscillator radio and all peripherals off 3.0 ma arm ? cortex tm - m3, ram, and f lash memory sleep current 25c, 1.8 v memory and 1.25 v core arm ? cortex tm - m3 sleeping, cpu clock set to 6 mhz from the high frequency rc oscillator radio and all peripherals off 2.0 ma serial controller current for each controller at maximum data rate 0.2 ma general purpose timer current for each timer at maximum clock rate 0.25 ma general purpose adc current at maximum sample rate, dma enabled 1.1 ma rx current radio receiver, mac, and baseband arm ? cortex tm - m3 sleeping, cpu clock set to 12 mhz 22.0 ma total r x current ( = i radio receiver, mac and baseband, cpu + i ram, and flash memory ) 25c , vdd_pads=3.0 v arm ? cortex tm - m3 running at 12 mhz 25.5 ma 25c , vdd_pads=3.0 v arm ? cortex tm - m3 running at 24 mhz 26.5 ma boost mode t otal r x current ( = i radio receiver, mac and baseband, cpu + i ram, and flash memory ) 25c , vdd_pads=3.0 v arm ? cortex tm - m3 running at 12 mhz 27.5 ma 25c , vdd_pads=3.0 v arm ? cortex tm - m3 running at 24 mhz 28.5 ma 2 -3 120 - 035x - 000 rev. 1.2 final
EM351 / em357 parameter test conditions min. typ. max. unit tx current radio transmitter, mac, and baseband 25c and 1.8 v core; max. power out (+3 dbm typical) arm ? cortex tm - m3 sleeping , cpu clock set to 12 mhz 26.0 ma total tx current ( = i radio transmitter, mac and baseband, cpu + i ram, and flash memory ) 25c , vdd_pads=3.0 v ; maximum power setting (+8 dbm); arm ? cortex tm - m3 running at 12 mhz 42.5 ma 25c , vdd_pads=3.0 v; +3 dbm power setting; arm ? cortex tm - m3 running at 12 mhz 30.0 ma 25c , vdd_pads=3.0 v ; 0dbm power setting; arm ? cortex tm - m3 running at 12 mhz 27.5 ma 25c , vdd_pads=3.0 v; minimum power setting; arm ? cortex tm - m3 running at 12 mhz 21.5 ma 25c , vdd_pads=3.0 v ; maximum power setting (+8 dbm); arm ? cortex tm - m3 running at 24 mhz 43.5 ma 25c , vdd_pads=3.0 v; +3 dbm power setting; arm ? cortex tm - m3 running at 24 mhz 31.0 ma 25c , vdd_pads=3.0 v ; 0 dbm power setting; arm ? cortex tm - m3 running at 24 mhz 28.5 ma 25c , vdd_pads=3.0 v; minimum power setting; arm ? cortex tm - m3 running at 24 mhz 22.5 ma 2 -4 120 - 035x - 000 rev. 1.2 final
EM351 / em357 figure 2 - 1 shows the variation of current in transmit mode (with the arm ? cortex tm - m3 running at 12 mhz). figure 2 - 1 . transmit power consumption 2 -5 120 - 035x - 000 rev. 1.2 final
EM351 / em357 figure 2 - 2 shows typical output power ag ainst power setting on the silicon labs reference design. figure 2 - 2 . transmit output power 2.5 digital i/o specifications table 2 - 5 lists the digital i/o s pecifications for the em3 5 x . the digital i/o power (named vdd_pads) comes from three dedicated pins (pins 23 , 28 and 37 ). the voltage applied to these pins sets the i/o voltage . table 2 - 5 . digital i/o specifications parameter test conditions min. typ. max. unit voltage supply (regulator input voltage) 2.1 3.6 v low schmitt switching threshold v swil schmitt input threshold going from high to low 0 .42 x vdd_pads 0.50 x vdd_pads v high schmitt switching threshold v swih schmitt input threshold going from low to high 0 .62 x vdd_pads 0.80 x vdd_pads v input current for logic 0 i il - 0.5 a input current for logic 1 i ih + 0.5 a 2 -6 120 - 035x - 000 rev. 1.2 final
EM351 / em357 parameter test conditions min. typ. max. unit input pull - up resistor value r ipu 24 29 34 k ? input pull - down resistor value r ipd 24 29 34 k ? output voltage for logic 0 v ol ( i ol = 4 ma for standard pads, 8 ma for high current pads) 0 0.18 x vdd_pads v output voltage for logic 1 v oh ( i oh = 4 ma for standard pads, 8 ma for high current pads) 0.82 x vdd_pads vdd_pads v output source current (standard current pad) i ohs 4 ma output sink current (standard current pad) i ols 4 ma output source curren t high current pad: pa6, pa7, pb6, pb7, pc0 i ohh 8 ma output sink current high current pad: pa6, pa7, pb6, pb7, pc0 i olh 8 ma total output current (for i/o pads) i oh + i ol 40 ma table 2 - 6 lists the nreset pin s pecifications for the em3 5 x . the digital i/o power (named vdd_pads) comes from three dedicated pins ( p ins 23 , 28 and 37 ). the voltage applied to these pins sets the i/o voltage . table 2 - 6 . nreset pin specifications parameter test conditions min. typ. max. unit low schmitt switching threshold v swil schmitt input threshold going from high to low 0 .42 x vdd_pads 0.50 x vdd_pads v high schmitt switching threshold v swih schmitt input threshold going from low to high 0 .62 x vdd_pads 0.80 x vdd_pads v input current for logic 0 i il - 0.5 a input current for logic 1 i ih + 0.5 a input pull - up resistor value r ipu pull - up value while the chip is not reset 24 29 34 k ? input pull - up resistor value r ipu reset pull - up value while the chip is reset 12 14.5 17 k ? 2 -7 120 - 035x - 000 rev. 1.2 final
EM351 / em357 2.6 non - rf system electrical characteristics table 2 - 6 lists the non - rf system level characteristics for the em3 5 x . table 2 - 7 . non - rf system specifications parameter test conditions min. typ. max. unit system wake time from deep sleep from wakeup event to first arm ? cortex tm - m3 instruction running from 6 mhz internal rc clock includes supply ramp time and oscillator startup time 110 s shutdown time going into deep sleep from last arm ? cortex tm - m3 instruction to deep sleep mode 5 s 2.7 rf electrical characteristics 2.7.1 receive table 2 - 7 lists the key parameters of the integrated ieee 802.15.4 - 2003 receiver on the em35x. note: receive measurements were collected with the em35x ceramic balun reference design (version a0) at 2440 mhz. the typical number indicates one standard deviation above the mean, measured at room temperature (25 c). the min and max numbers were measured over process corners at room temperature table 2 - 8 . receive c haracteristics parameter test conditions min. typ. max. unit frequency range 2400 2500 mhz sensitivity (boost mode) 1% per, 20 byte packet defined by ieee 802.15.4 - 2003 - 102 - 9 6 dbm sensitivity 1% per, 20 byte packet defined by ieee 802.15.4 - 2003 - 100 - 94 dbm high - side adjacent channel rejection ieee 802.15.4 - 2003 interferer signal , wanted ieee 802.15.4 - 2003 signal at - 82 dbm 35 db low - side adjacent channel rejection ieee 802.15.4 - 2003 interferer signal , wanted ieee 802.15.4 - 2003 signal at - 82 dbm 35 db 2 nd high - side adjacent channel rejection ieee 802.15.4 - 2003 interferer signal , wanted ieee 802.15.4 - 2003 signal at - 82 dbm 4 6 db 2 nd low - side adjacent channel rejection ieee 802.15.4 - 2003 interferer signal , wanted ieee 802.15.4 - 2003 signal at - 82 dbm 4 6 db high - side adjacent channel rejection filtered ieee 802.15.4 - 2003 interferer signal , wanted ieee 802.15.4 - 2003 signal at - 82 dbm 3 9 db low - side adjacent channel rejection filtered ieee 802.15.4 - 2003 interferer signal , wanted ieee 802.15.4 - 2003 signal at - 82 dbm 47 db 2 -8 120 - 035x - 000 rev. 1.2 final
EM351 / em357 parameter test conditions min. typ. max. unit 2 nd high - side adjacent channel rejection filtered ieee 802.15.4 - 2003 interferer signal , wanted ieee 802.15.4 - 2003 signal at - 82 dbm 4 9 db 2 nd low - side adjacent channel rejection filtered ieee 802.15.4 - 2003 interferer signal , wanted ieee 802.15.4 - 2003 signal at - 82 dbm 4 9 db high - side adjacent channel rejection cw interferer signal , wanted ieee 802.15.4 - 2003 signal at - 82 dbm 44 db low - side adjacent channel rejection cw interferer signal , wanted ieee 802.15.4 - 2003 signal at - 82 dbm 47 db 2 nd high - side adjacent channel rejection cw interferer signal , wanted ieee 802.15.4 - 2003 signal at - 82 dbm 59 db 2 nd low - side adjacent channel rejection cw interferer signal , wanted ieee 802.15.4 - 2003 signal at - 82 dbm 59 db channel rejection for all other channels ieee 802.15.4 - 2003 interferer signal , wanted ieee 802.15.4 - 2003 signal at - 82 dbm 40 db 802.11g rejection centered at + 12 mhz or - 13 mhz ieee 802.15.4 - 2003 interferer signal , wanted ieee 802.15.4 - 2003 signal at - 82 dbm 3 6 db maximum input signal level for correct operation 0 dbm co - channel rejection ieee 802.15.4 - 2003 interferer signal , wanted ieee 802.15.4 - 2003 signal at - 82 dbm - 6 dbc relative frequency error ( 50% greater than the 2x40 ppm required by ieee 802.15.4 - 2003 ) - 120 +120 ppm relative timing error ( 50% greater than the 2x40 ppm required by ieee 802.15.4 - 2003 ) - 120 +120 ppm linear rssi range as defined by ieee 802.15.4 - 2003 40 db rssi range - 90 - 4 0 db m 2 -9 120 - 035x - 000 rev. 1.2 final
EM351 / em357 figure 2 - 3 shows the variation of receive sensitivity with temperature for boost mode and normal mode for a typical chip. figure 2 - 3 . receive sensitivity vs temperature 2.7.2 transmit table 2 - 8 lists the key parameters of the integrated ieee 802.15.4 - 2003 transmitter on the em35x. note: transmit measurements were collected with the em35x ceramic balun reference design (version a0 ) a t 2440 mhz. the typical number indicates one standard deviation below the mean, measured at room temperature (25 c). the min and max numbers were measured over process corners at room temperature. in terms of impedance, this reference design presents a 3n3 indu ctor in parallel with a 100 :50 balun to the rf pins. 2 -10 120 - 035x - 000 rev. 1.2 final
EM351 / em357 table 2 - 9 . transmit characteristics parameter test conditions min. typ. max. unit maximum output power (boost mode) at highest boost mode power setting (+8) 8 dbm maximum output power at highest normal mode power setting (+3) 1 5 dbm minimum output power at lowest power setting - 55 dbm error vector magnitude (offset - evm) as defined by ieee 802.15.4 - 2003 , which sets a 35% maximum 5 15 % carrier frequency error - 40 +40 ppm psd mask relative 3.5 mhz away - 20 db psd mask absolute 3.5 mhz away - 30 dbm figure 2 - 4 shows the variation of transmit power with temperature for maximum boost mode power, and normal mode for a typical chip. figure 2 - 4 . transmit p ower vs temperature 2 -11 120 - 035x - 000 rev. 1.2 final
EM351 / em357 2.7.3 synthesizer table 2 - 9 lists the key parameters of the integrated synthesizer on the em35x. table 2 - 10 . synthesizer characteristics parameter test conditions min. typ. max. unit frequency range 2400 2500 mhz frequency resolution 11.7 khz lock time from off 100 s relock time channel change or r x /t x turnaround (ieee 802.15.4 - 2003 defines 192 s turnaround time) 100 s phase noise at 100 khz offset - 7 5 dbc/hz phase noise at 1 mhz offset - 100 dbc/hz phase noise at 4 mhz offset - 1 08 dbc/hz phase noise at 10 mhz offset - 114 dbc/hz 2 -12 120 - 035x - 000 rev. 1.2 final
EM351 / em357 3 top - level functional description figure 3 - 1 shows a detailed block diagram of the em35 x . figure 3 - 1 . em35 x block diagram adc rf _ p , n program f lash 1 28 / 192 k b data ram 12 kb hf crystal osc lf crystal osc general purpose adc serial wire and jtag debug i nternal lf rc - osc g pio multiplexor switch chip manage r 1 . 8 v regulator bias 2 nd level interrupt controller rf _ tx _ alt _ p , n osca oscb pa [ 7 : 0 ] , pb [ 7 : 0 ] , pc [ 7 : 0 ] encryption acclerator if always powered domain arm ? cortex tm - m 3 cpu with nvic and mpu vreg _ out watchdog pa select lna pa pa dac mac + baseband sleep timer por nreset general purpose timers gpio registers uart / spi / twi synth i nternal hf rc - osc tx _ active swclk , jtck calibration adc packet trace cpu debug tpiu / itm / fpb / dwt 1 . 25 v regulator vdd _ core the em35 x radio receiver is a low - if, super - heterodyne receiver. the architecture has been chosen to optimize co - existence with other devices in the 2.4 ghz band (namely w i - fi and bluetooth), and to minimize power consumption. the receiver uses differential signal paths to reduce sensitivity to noise interference. following rf amplification, the signal is downconverted by an image - rejecting mixer, filtered , and then digitized by an adc. the digital section of the receiver uses a coherent demodulator to generate symbols for the hardware - based m ac. t he digital receiver also contains the analog radio calibration routines , and control s the gain within the receiver path. the radio transmitter uses an efficient architecture in which the data stream directly modulates the vco frequency. an integrated pa provides the output power. digital logic controls tx path and output power calibration . if the em35 x is to be used with an external pa, use the tx_active or ntx_active signal to control the timing of the external switching logic. the integrated 4.8 ghz vco and loop filter minimize off - chip circuitry. only a 24 mhz crystal with its loading capacitors is required to establish th e pll local oscillator signal. the mac interfaces the on - chip ram to the rx and tx baseband modules. the mac provides hardware - based ieee 802.15.4 - 2003 packet - level filtering. it supplies an accurate symbol time base that minimizes the synchronization effo rt of the ember software and meets the protocol timing requirements. in addition, it provides timer and synchronization assistance for the ieee 802.15.4 - 2003 csma - ca algorithm. the em35 x integrates hardware support for a p acket t race module, which allows robust packet - based debug. this element is a critical component of ember desktop, the ember development environment , and provid es advanced network debug capability when used with the ember debug adapter (isa3) . 3 -1 120 - 035x - 000 rev. 1.2 final
EM351 / em357 the em35 x integrates an a rm ? cortex tm - m3 micr oprocessor , revision r1p1 . this industry - leading core provides 32- bit performan ce and is very power - efficient. it has excellent code density using the arm ? thumb - 2 instruction set. the processor can be operated at 12 mhz or 24 mhz when using the high - frequency crystal oscillator, or at 6 mhz or 12 mhz when using the high - frequency internal rc oscillator. the em35 1 has 128 kb of flash memory and the em357 has 192 kb of flash memory. both chips have 12 kb of ram on - chip , and the arm configurable mem ory protection unit (mpu) . the em35 x implements both the arm s erial w ire and jtag debug interfaces . these interfaces provide real time, non - intrusive programming and debugging capabilities. serial wire and jtag provide the same functionality, but are mutua lly exclusive. the s erial w ire interface uses two pins ; the jtag interface uses f ive . s erial w ire is preferred , since it uses fewer pins. the em35 x contains 24 gpio pins shared with other peripheral or alternate functions. because of f lexible routing within the em35 x , external devices can use the alternate functions on a variety of different gpios. the integrated s erial c ontroller sc1 can be configured for spi (master or slave ), twi (master - only), or uart operation , and the s erial c ontroller sc2 can be configured for spi (master or slave) or twi (master - only) operation. the em35 x has a g eneral p urpose adc which can sample analog signals from six gpio pins in single - ended or differential modes . it can also sample the 1.8 v regulated supply vdd_padsa, the voltage reference vref, and gnd. the adc has one voltage range : 0 v to 1.2 v (normal) . the adc has a dma mode to capture samples and automat ically transfer them into ram. the integrated voltage reference for the adc , vref , c an be made available to externa l circuitry. an external voltage reference can also be driven into the adc. the regulator input voltage, vdd_pads, can not be measured using the general purpose adc, but it can be measured through ember software. the em 35x contains four oscillators: a high - frequency 24 mhz external crystal oscillator , a high - frequency 12 mhz internal rc oscillator, an optional low - frequency 32.768 khz external crystal oscillator , and a low - frequency 10 khz internal rc oscillator. the em35 x has an ultra low power , deep sleep state w ith a choice of clocking modes. the sleep timer can be clocked with either the external 32.768 khz crystal oscillator or with a 1 khz clock derived from the internal 10 khz rc oscillator. alternatively , all clocks can be disab led for the lowest powe r mode. in the lowest power mode, only external events on gpio pins will wake up the chip . the em35 x has a fast startup time (typically 110 s) from deep sleep to the execution of the first arm ? cortex tm - m3 instruction. the em35 x contains three power domains. the always - on high voltage supply powers the gpio pads and critical chip functions. regulated low voltage supplies power t he rest of the chip . the low voltage supplies are disabled during deep sleep to reduce power consumptio n. integrated voltage regulators generate regulated 1.2 5 v and 1.8 v voltages from an unregulated supply voltage. the 1.8 v regulator output is decoupled and routed externally to supply analog blocks, ram, and flash memo ries. the 1.2 5 v regulator output is decoupled externally and supplies the core logic. note: the em35 x is not pin - compatible with the previo us generation chip, the em250 , except for the rf section of the chip. p ins 1 - 11 and 45 - 48 are compatible , to ease migration to the em35 x . 3 -2 120 - 035x - 000 rev. 1.2 final
EM351 / em357 4 radio module the radi o module consists of an analog front end and digital baseband as shown in figure 3 - 1, em35 x block diagram in chapter 3, top level functional description . 4.1 receive (rx ) path the r x path uses a low - if, super - heterodyne receiver that rejects the image frequency using complex mixing and polyphase filtering . in the analog domain , the input rf signal from the antenna is first amplified and mixed down to a 4 mhz if fre quen cy. the mixers? output is filtered, combined , and amplified before being sam pled by a 12 msps adc. the digitized signal is then demodulated in the digital baseband. the filtering within the r x path improves the em35 x ?s co - existence with other 2.4 ghz trans ceivers such as zigbee/ 802.15.4 - 2003 , ieee 802.11 - 2007 , and bluetooth radios . the digital baseband also provides gain control of the r x path , both to enable the reception of small and large wanted signals and to tolerate large interferers. 4.1.1 rx baseband the em35 x r x digital baseb and implements a coherent demodulator for optimal performance. the baseband demodulates the o - qpsk signal at the chip level and synchron izes with the ieee 802.15.4 - 2003 - defined preamble. an automatic gain control (agc) module adjusts the analog gain continuously every ? symbol until the preambl e is detected. once detected, the gain is fixed for the remainder of the packet . the baseband despreads the demodulated data into 4 - bit symbols. these symbols are buffered and passed to the hard ware - based mac module for packet assembly and filtering. in addition, the r x baseband provides the calibration and control interface to the analog r x modules , including the lna, r x baseband f ilter, and mo dulation modules. the ember s oftware includes calibration algorithms that use this interface to reduce the effects of silicon process and temperature variation. 4.1.2 rssi and cca the em35 x calculates the rssi over every 8 - symbol period as well as at the end of a received packet. the linear range o f rssi i s specified to be at least 40 db over temperature . at room temperature, the linear range is ap proximately 60 db ( - 90 dbm to - 30 dbm input signal ). the em35 x r x baseband provides support for the ieee 802.15.4 - 2003 rssi cca method . clear channel rep orts busy medium if rssi exceeds its threshold. 4.2 transmit (tx ) path the em35 x t x path produces an o - qpsk - modulated signal using the analog fron t e nd and digital baseband . the area - and power - efficient t x architecture uses a two - point modulat ion scheme to modulate the rf signal generated by the synthesizer. the modu lated rf signal is fed to the integrated pa and then out of the em35 x . 4.2.1 tx baseband the em35 x t x baseband in the d igital d omain spreads the 4 - bit symbol into its ieee 802.15.4 - 2003 - defined 32 - chi p sequence. it also provides the interface for the ember software to calibrate the t x module to reduce silicon process, temperature, and voltage variations. 4.2.2 tx_active and ntx_active signal s for appli cations requiring an external pa , two signal s are provided called tx_active and ntx_active . these signals are the inverse of each other. they can be used for external pa power management and rf s witching logic. i n transmit mode the tx b aseband drives tx_active high , as describe d in table 7 - 5, gpio signal assignments . i n receive mode the tx_active signal is low. t x_active is t he alternate function of pc5 , and 4 -1 120 - 035x - 000 rev. 1.2 final
EM351 / em357 ntx_active is the alternate function of pc6 . see c hapter 7 gpio fo r details of the alternate gpio functions. the digital i/o that provide these signa ls have a 4 ma output sink and source capability. 4.3 calibration t he ember s oftware calibrates the radio using dedicated hardware r e sources. 4.4 integrated mac module the em35 x integrates most of the ieee 802.15.4 - 2003 mac requirements in hardware. this allows the arm ? cortex tm - m3 cpu to provide greater bandwidth to application and network operations. in addition, the hardware acts as a first - line filter for unwanted packets. the em35 x mac us es a dma inter face to ram to further reduce the overall arm ? cortex tm - m3 cpu interaction when transmitting or receiving packets. when a packet is ready for transmission , the ember software configures the tx mac dma by indicating the packet buffer ram location. the mac waits for the backoff period, the n switche s the baseband to tx mode and performs channel assessment. wh en the channel is clear the mac reads data from the ram buffer, calculates the crc, and provides 4 - bit symbols to the baseband. when the final byte has been read and s ent to the baseband, the crc remainder is read and transmitted. the mac i s in r x mode m ost of the time . in rx mode various format and address filters keep unwanted packets f rom using excessive ram buffers, and prevent the cpu from being unnecessarily inte rrupted. when the recep tion of a packet begins , the mac reads 4 - bit symbols from the baseband and calculates the crc. it then assembles the received dat a for storage in a ram buffer. r x mac dma provides direct access to ram . on ce the packet has been receiv ed additional data , which provides statistic al information on the packet to the ember software , is appended to the end of the packet in the ram buffer space . the primary features of the mac are: ? crc g eneration, appending, and checking ? hardware timers and interrupts to achieve the mac symbol timing ? automatic prea mble and sfd pre - pending on tx packet s ? address recognition and packet filtering on rx packets ? automatic acknowledgement transmission ? automatic transmission of packets from memory ? automatic transmission after backoff time if channel is clear (cca) ? automatic acknowledgement checking ? time stamping received and transmitted messages ? attaching packet information to received packets (lqi, rssi, gain, time stamp, and packet status) ? ieee 8 0 2.15.4 - 2003 timing and slotted/unslotted timing 4.5 packet trace interface (pti) the em35 x integrates a true phy - level pti for effective network - level debugging. it monitors all the phy tx and r x pac kets between the mac and baseband modules without affecting their normal operation . it cannot be used to inject packets into the phy/mac interface . this 500 kbps asynchronous inter face comprises the frame signal (p ti _en , pa4 ) and the data signal (p ti _data , pa5 ). pti is supported by the ember d evelopment tools . 4.6 rand om number generator thermal noise in the analog circuitry is digitized to provide entropy for a true random number generator (trng). the trng produces 16 - bit uniformly distributed numbers. the ember software uses the trng to seed a pseudo random number generator ( p rn g ). the trng is also used directly for cryptographic key generation. 4 -2 120 - 035x - 000 rev. 1.2 final
EM351 / em357 5 arm ? cortex ?- m3 and memory modules this chapter discusses the arm ? cortex tm - m3 microprocessor, and reviews the em 35x ?s f lash and ram memory modules as well as the memory protection unit (mpu). 5.1 arm ? cortex ?- m3 microprocessor the em 35x integrates the arm ? cortex tm - m3 microprocessor , revision r1p1, developed by arm ltd . , making the em 35x a true s ystem - on - c hip solution. the arm ? cortex tm - m3 is a n advanced 32 - bit modified harvard architecture processor that has separate internal program and data buses , but presents a unified program and data address space to software . the word width is 32 bits for both the program and data sides . the arm ? cortex tm - m3 allows unaligned word a nd half - word data accesses to support efficiently - packed data structures. the arm ? cortex tm - m3 clock speed is configurable to 6 mh z, 12 mhz , or 24 mhz . for normal operation 24 mhz is preferred over 12 mhz due to improved performance for all applications and improved duty cycling for applications using sleep modes . the 6 mhz operation can only be used when radio operations are not required since the radio requires an accurate 12 mhz clock . the arm ? cortex tm - m3 in t he em 35x has also been enhanced to support two separate memory protection levels. basic protection is available without using the mpu , but normal operation uses the mpu. the mpu allows for protecting unimplemented areas of the memory map t o prevent common software bugs from interfering with software operation . the architecture could also allow for separation of the networking stack from the application code using a fine granularity ram protection module. e rrant writes are captured and details are reported to the developer to assist in tracking down and fixing issues. 5 -1 120 - 035x - 000 rev. 1.2 final
EM351 / em357 5.2 embedded memory figure 5 - 1 shows the EM351 arm ? cortex tm - m3 memory map and figure 5 - 2 shows the em357 arm ? cortex tm - m3 memory map . figure 5 - 1 . EM351 arm ? cortex tm - m3 memory map main flash block ( 128 kb ) lower mapping (normal mode) 0x00000000 0x0001ffff ram (12kb) mapped onto system interface 0x20000000 0x20002fff ram bit band alias region mapped onto system interface (not used) 0x22000000 0x22002000 flash ram peripheral registers mapped onto system interface register bit band alias region mapped onto system interface (not used) 0x40000000 0x40000xxx 0x42000000 0x42002xxx not used private periph bus (internal ) not used private periph bus (external) not used not used not used 0xe0000000 itm dwt fpb nvic tpiu rom table 0xe0001000 0xe0002000 0xe0003000 0xe000e000 0xe000f 000 0xe003ffff 0xe0040000 0xe0041000 0xe0042000 0xe00 ff000 0xe00fffff 0xe0000000 0x00000000 0x20000000 0x40000000 0x60000000 0xa0000000 0xffffffff 0xdfffffff 0x9fffffff 0x5fffffff 0x3fffffff 0x1fffffff fixed info block (2kb) 0x08040000 0x080407ff 0x08040f ff 0x08040800 main flash block (128kb) upper mapping (boot mode) 0x08000000 0x0801ffff fixed info block (2kb) optional boot mode maps fixed info block to the start of memory 0x000007ff not used not used customer info block (2kb) 5 -2 120 - 035x - 000 rev. 1.2 final
EM351 / em357 figure 5 - 2 . em357 arm ? cortex tm - m3 memory map main flash block ( 192 kb ) lower mapping (normal mode) 0x00000000 0x0002ffff ram (12kb) mapped onto system interface 0x20000000 0x20002fff ram bit band alias region mapped onto system interface (not used) 0x22000000 0x22002000 flash ram peripheral registers mapped onto system interface register bit band alias region mapped onto system interface (not used) 0x40000000 0x40000xxx 0x42000000 0x42002xxx not used private periph bus (internal ) not used private periph bus (external) not used not used not used 0xe0000000 itm dwt fpb nvic tpiu rom table 0xe0001000 0xe0002000 0xe0003000 0xe000e 000 0xe000f000 0xe003ffff 0xe0040000 0xe 0041000 0xe 0042000 0xe00 ff000 0xe00fffff 0xe0000000 0x00000000 0x20000000 0x40000000 0x60000000 0xa0000000 0xffffffff 0xdfffffff 0x9fffffff 0x5fffffff 0x3fffffff 0x1fffffff fixed info block (2kb) 0x08040000 0x080407ff 0x08040fff 0x08040800 main flash block (192kb) upper mapping (boot mode) 0x08000000 0x0802ffff fixed info block (2kb) optional boot mode maps fixed info block to the start of memory 0x000007ff not used not used customer info block (2kb) 5 -3 120 - 035x - 000 rev. 1.2 final
EM351 / em357 5.2.1 flash mem ory 5.2.1.1 flash overview t he em35 1 provides a total of 132 kb of flash memory and the em357 provides a total of 196 kb of flash memory . the flash memory is provided in three separate blocks: ? main flash block (mfb) ? fixed information block (fib) ? customer information block (cib) the mfb is divided into 2048 - byte pages . the EM351 has 64 pages and the em357 has 96 pages. t he cib is a single 2048 - byte page . t he fib is a single 2048 - byte page. the smallest erasable unit is one page and the smallest writable unit is an aligned 16 - bit half - word . the flash is rated to have a guaranteed 20 ,000 write/erase cycles. the flash cell has been qualified f or a data retention time of >100 years at room temperature. flash may be programmed either through the serial wire/jtag interface or through bootloader software. programming flash through serial wire/j tag requires the assistance of ram - based utility code . p rogramming through a bootloader requires ember software for over - the - air loading or serial link loading. 5.2.1.2 main flash block the start of the mfb is mapped to both address 0x00000000 and address 0x08000000 in normal boot mode, but is mapped only to address 0 x08000000 in fib monitor mode (see also section 7.5, boot configuration in chapter 7, gpio ) . consequently, it is recommended that software intended to execute from the mfb is designed to operate from t he upper address, 0x08000000, since this address mappin g is always available in all modes. the mfb stores all program instructions and constant data. a small portion of the mfb is devoted to non - volatile token storage using the ember s imulated eeprom system. 5.2.1.3 fixed information block t he 2 k b fib is used to store fixed manufacturing data including serial numbers and calibration values . the start of the fib is mapped to address 0x08040000. this block can only be programmed during production by silicon labs . the fib also contains a monitor program, which is a s erial - link - only way of performing low - level memory accesses . in fib monitor mode (see section 7.5, boot configuration in chapter 7, gpio) , the start of the fib is mapped to both address 0x00000000 and address 0x08040000 so the monitor may be executed out of reset . 5.2.1.4 customer information block the 2048 byte cib can be used to store customer data . th e start of the cib is mapped to address 0x08040800. the cib cann ot be executed. the f irst eight half - words of t he cib are dedicated to special storage called optio n bytes. an option byte is a 16 bit quantity of flash where the lower 8 bits contain the data and the upper 8 contain the inverse of the lower 8 bits. the upper 8 bits are automatically generated by hardware and cannot be written to by the user , see table 5 - 1 . the option byte hardware also verifies the inverse of each option byte when exiting from reset and generates an error, which prevents the cpu from executing code, if a discrepancy is found. all of this is transparent to the user. 5 -4 120 - 035x - 000 rev. 1.2 final
EM351 / em357 table 5 - 1 . option byte storage address bits [15:8] bits [7:0] notes 0x08040800 inverse option byte 0 option byte 0 configures flash read protection 0x08040802 inverse option byte 1 option byte 1 reserved 0x08040804 inverse option byte 2 option byte 2 available for customer use 1 0x08040806 inverse option byte 3 option byte 3 available for customer use 1 0x08040808 inverse option byte 4 option byte 4 configures flash write protection 0x0804080a inverse option byte 5 option byte 5 configures flash write protection 0x0804080c inverse option byte 6 option byte 6 configures flash write protection 2 0x0804080e inverse option byte 7 option byte 7 reserved 1 option bytes 2 and 3 do not link to any specific hardware functionality other than the option byte loader. therefore, they are best used for storing data that requires a hardware verification of the data integrity. 2 option byte 6 i s r eserved /unused in the EM351 due to the smaller flash size. table 5 - 2 shows the mapping of the option bytes that are used for read and write protection of the flash. each bit of the flash write protection option bytes protects a 4 page region of the main flash block. the EM351 has 16 regions and therefore o ption b ytes 4 and 5 control flash write protection ( o ption b yte 6 is reserved/unused) . the em357 has 24 regions and therefore o ption b ytes 4, 5, and 6 control flash write protection. these write protection bits are active low, and therefore the erased state of 0xff disables write protection. like read protection, write protection only take s effect after a reset. write protection not only prevents a write to the region, but also prevent s page erasure. option byte 0 controls f lash read protection . when option byte 0 is set to 0xa5 , read protection is disabled. all other values, including the erased state 0xff, enable read protection when coming out of reset . the internal state of read pr otection (active versus disabled) can only be changed by applying a full chip reset. if a debugger is connected to the em35x , th e intrusion state is latched. r ead protection is com bined with this latched intrusion signal . when both read protection and intrusion are set, all flash is disconnected from the internal bus. as a side effect, the cpu cannot execute code since all flash is disconnected from the bus. this functionality prevents a debug tool from being able to read the contents of any flash. the only means of clearing the intrusion signal is to disconnect the debugger and reset the entire chip using the nreset pin. by requiring a chip reset, a debugger cannot install or execute malicious code that could allow the contents of the flash to be read . the only way to disable read protection is to program option byte 0 with the value 0xa5 . o ption byte 0 must be erased before it can be programmed. e rasing option byte 0 while read protection is active automatically mass - erases the main flash block. by aut omatically erasing main flash, a debugger cannot disable read protection and readout the contents of main flash without destroying its contents . note: when read protection is active, the bottom four flash pages, addresses 0x08000000 to 0x08001fff , are automatic ally write - protected . w rite protecting the bottom four flash pages of main flash prevents an attacker from reprogram ming the reset vector and execut ing arbitrary code. in general, if read protection is active then write protection should also be active. this prevent s an attacker from reprogramming flash with malicious code that could readout the flash after the debugger is disconnected. even though read protection automatically protects the reset vector, the same technique of reprogramming flash could be performed at an address outside the bottom four flash pages . to obtain fully protected flash, both read protection and write protection should be active. 5 -5 120 - 035x - 000 rev. 1.2 final
EM351 / em357 table 5 - 2 . option byte write protection bit map option byte bit notes option byte 0 bit [7:0] read protection of all flash (mfb, fib, cib) option byte 1 b it [7:0] reserved for silicon labs use option byte 2 bit [7:0] available for customer use option byte 3 bit [7:0] available for customer use option byte 4 bit [0] write protection of address range 0x08000000 ? 0x0800 1 fff bit [1] write protection of address range 0x0800 2 000 ? 0x0800 3 fff bit [2] write protection of address range 0x0800 4 000 ? 0x0800 5 fff bit [3] write protection of address range 0x0800 6 000 ? 0x0800 7 fff bit [4] write protection of address range 0x0800 8 000 ? 0x0800 9 fff bit [5] write protection of address range 0x0800 a 000 ? 0x0800 b fff bit [6] write protection of address range 0x0800 c 000 ? 0x0800 d fff bit [7] write protection of address range 0x0800 e 000 ? 0x0800 f fff option byte 5 bit [0] write protection of address range 0x080 10 000 ? 0x080 11 fff bit [1] write protection of address range 0x080 12 000 ? 0x080 13 fff bit [2] write protection of address range 0x080 14 000 ? 0x080 15 fff bit [3] write protection of address range 0x080 16 000 ? 0x080 17 fff bit [4] write protection of address range 0x080 18 000 ? 0x080 19 fff bit [5] write protection of address range 0x080 1a 000 ? 0x080 1b fff bit [6] write protection of address range 0x080 1c 000 ? 0x080 1d fff bit [7] write protection of address range 0x080 1e 000 ? 0x080 1f fff option byte 6 1 bit [0] write protection of address range 0x080 20 000 ? 0x080 21 fff bit [1] write protection of address range 0x080 22 000 ? 0x080 23 fff bit [2] write protection of address range 0x080 24 000 ? 0x080 25 fff bit [3] write protection of address range 0x080 26 000 ? 0x080 27 fff bit [4] write protection of address range 0x080 28 000 ? 0x080 29 fff bit [5] write protection of address range 0x080 2a 000 ? 0x080 2b fff bit [6] write protection of address range 0x080 2c 000 ? 0x080 2d fff bit [7] write protection of address range 0x080 2e 000 ? 0x080 2f fff option byte 7 bit [7:0] reserved for silicon labs use 1 option byte 6 is reserved/unused in the EM351 due to the smaller flash size. 5 -6 120 - 035x - 000 rev. 1.2 final
EM351 / em357 5.2.1.5 simulated eeprom ember software reserves 8 kb of the main flash block as a s imulated eeprom storage area for stack and customer tokens. the s imulated eeprom storage area implements a wear - leveling algorithm to extend the number of s imu lated eeprom write cycles beyond the physical limit of 20,000 write cycles for which each flash cell is qualified. 5.2.2 ram 5.2.2.1 ram overview the em35 x has 12 kb of static ram on - chip . th e start of ram is mapped to address 0x20000000 . although the arm ? cortex tm - m3 allows bit band accesses to this address region , the standard mpu configuration does not permit use of the bit - band feature. the ram is physically connected to the ahb system bus and is therefore accessible to both the arm ? cortex tm - m3 m icroprocessor and the debugger. the ram can be accessed for both instruction and data fetches as bytes, half words , or words . t he standard mpu configuration does not permit execution from the ram, but for special purposes the mpu may be disabled . to the bu s , the ram appears as 32 - bit wide memory and in most situations has zero wait state read or write access. in the higher cpu clock mode the ram requires two wait states. this is handled by hardware transparent to the user application with no configuration r equired. 5.2.2.2 direct memory access (dma) to ram several of the peripherals are equipped with dma controllers allowing them to transfer data into and out of ram autonomously. this applies to the radio (802.15.4 - 2003 mac), g eneral p urpose adc, and both serial con trollers. in the case of the serial controllers , the dma is full duplex so that a read and a write to ram may be requested at the same time. thus there are six dma channels in total. see chapter 8, section 8.7 and chapter 10, section 10.1.4 fo r a description of how to configure the serial controllers and adc for dma operation. t he dma channels do not use ahb s ystem bus bandwidth as they access the ram directly. the em35 x integrates a dma arbiter that ensures fair access to the microprocessor a s well as the peripherals through a fixed priority scheme appropriate to the memory bandwidth requirements of each master. the priority scheme is as follows, with the top peripheral being the highest priority: 1. general purpose adc 2. serial controller 2 receiv e 3. serial controller 2 transmit 4. mac 5. serial controller 1 receive 6. serial controller 1 transmit 5.2.2.3 ram memory protection the em35 x integrates two memory protection mechanisms. the first memory protection mechanism is through the arm ? cortex tm - m3 memory protection unit (mpu) described in the memory protection unit section. the mpu may be used to protect any area of memory . mpu configuration is normally handled by ember software . the second memory protection mechanism is through a fine granularity ram protection module. this allows segmentation of the ram into 32 - b yte blocks where any block can be marked as write protected. an attempt to write to a protected ram block using a user mode write results in a bus error being signaled on the ahb system bus. a privilege d mode write is allowed at any time and reads are allowed in either mode. the main purpose of this fine granularity ram protection module is to notify th e software of erroneous writes to system areas of memory. ram protection is configured using a group of registers that provide a bit map. each bit in the map represents a 32 - b yte block of ram . w hen the bit is set the block is write - protected. the fine gra nularity ram memory protection mechanism is also available to the peripheral dma controllers. a register bit enable s protection from dma writes to protected memory. if a dma write is made to a protected location in ram , a management interrupt is generated. at the same time the faulting address and the 5 -7 120 - 035x - 000 rev. 1.2 final
EM351 / em357 identification of the peripheral is captured for later debugging. note that only peripherals capable of writing data to ram , such as received packet data or a received serial port character , can generate this interrupt. 5.2.3 registers appendix a, register address table provides a short description of all application - accessible registers within the em35 x . complete descriptions are provided at the end of each applicable peripheral?s description . the registers are mapped to the system address space starting at address 0x4000000 0 . these registers allow for the control and configuration of the various peripherals and modules. the cpu only performs word - aligned accesses on the system bus. the cpu perform s a word aligne d read - modify - write for all byte, half - word , and unaligned writes and a word - aligned read for all reads. silicon labs recommends accessing all peripheral registers using word - aligned addressing. as with the ram, the peripheral registers fall within an address range that allows for bit - band access by the arm ? cortex tm - m3 , but the standard mpu configuration does not allow access to this alias address range. 5.3 memory protection unit the em35 x includes the arm ? cortex tm - m3 memory protection unit , o r mpu. the mpu controls access rights and characteristics of up to eight address regions , each of which may be divided into eight equal sub - regions. refer to the arm ? cortex tm - m3 technical reference manual (ddi 0337a) for a detailed description of the mpu. ember software configures the mpu in a standard configuration and application software should no t modify it . the configuration is designed for optimal detect ion of illegal instruction or data accesses. i f an illegal access is attempted , the mpu captures information about the access type, the address being accessed , and the location of the offending software. this simplifies software de bugging and increases the reliability of deployed devices. as a consequence of this mpu configuration , accessing r am and register bi t - band address al ias regions is not permitted, and generate s a bus fault if attempted. 5 -8 120 - 035x - 000 rev. 1.2 final
EM351 / em357 6 system modules system modules encompass power domains, resets, clocks, system timers, power management, and encryption. figure 6 - 1 shows these modules and how they interact. figure 6 - 1 . system module block diagram nreset vdd _ pads vreg _ out vdd _ core vdd _ mem por hv por lvcore por lvmem vreg _ 1 v 8 vreg _ 1 v 25 always - on supply mem supply core supply por lv por hv reset filter reset generation external regulator optional connections for external regulator oscrc osc 32 k div 10 clk 1 k clk 32 k osc 32 a osc 32 b jrst always - on domain poreset sysreset dapreset mem domain arm ? cortex ? - m 3 debug ahb - ap sysresetreq core domain arm ? cortex ? - m 3 cpu flitf option byte error flash ram osc 24 m oschf osca oscb clock switch sysclk cdbgrstreq power management watchdog sleep timer watchdog deep sleep wakeup reg _ en recomended connections for internal regulator preset hv preset lv registers registers security accelerator swj reset recording wakeup recording gpio wake monitoring pa 2 pb 2 irqd sleep timer compare b wake _ core c dbg pwrupreq csyspwrupreq sleep timer compare a sleep timer wrap 6 -1 120 - 035x - 000 rev. 1.2 final
EM351 / em357 6.1 power domains the em35x contain s three power domains: ? an ?always - on domain? containing all logic and analog cells required to manage the em35x?s power modes, including the gpio controller and sleep timer. this domain must remain powered. ? a ?core domain? containing the cpu, nested vector ed interrupt controller (nvic), and peripherals. to save power, this domain can be powered down using a mode called deep sleep. ? a ?memory domain? containing the ram and flash memories. this domain is managed by the power management controller. when in deep sleep, the ram portion of this domain is powered from the always - on domain supply to retain the ram contents while the regulators are disabled. during deep sleep the flash portion is completely powered down. 6.1.1 internally regulated power the preferred and re commended power configuration is to use the internal regulated power supplies to provide power to the core and memory domains. the internal regulators (vreg_1v25 and vreg_1v8) generate nominal 1.25 v and 1.8 v supplies. the 1.25 v supply is internally rout ed to the core domain and to an external pin. the 1.8 v supply is routed to an external pin where it can be externally routed back into the chip to supply the memory domain. the internal regulators are described in chapter 16, integrated voltage regulator. when using the internal regulators, the always - on domain must be powered between 2.1 v and 3.6 v at all four vdd_pads pins. when using the internal regulators, the vreg_1v8 regulator output pin (vreg_out) must be connected to the vdd_mem, vdd_padsa, vdd_v co, vdd_rf, vdd_if, vdd_pre, and vdd_synth pins. when using the internal regulators, the vreg_1v25 regulator output and supply requires a connection between both vdd_core pins. 6.1.2 externally regulated power optionally, the on - chip regulators may be left unuse d, and the core and memory domains may instead be powered from external supplies. for simplicity, the voltage for the core domain can be raised to nominal 1.8 v, requiring only one external regulator, or the core domain can be powered from the on - chip regu lators while the other domains are powered externally. note that if the core domain is powered at a higher voltage (1.8 v instead of 1.25 v) then power consumption increases. a regulator enable signal, reg_en, is provided for control of external regulators . this is an open - drain signal that requires an external pull - up resistor. if reg_en is not required to control external regulators it can be disabled (see section 7.3, forced functions in chapter 7, gpio) . using an external regulator requires the always - on domain to be powered between 2.1 v and 3.6 v at all four vdd_pads pins. when using an external regulator, the vreg_1v8 regulator output pin (vreg_out) must be left unconnected. when using an external regul ator, this external nominal 1.8 v supply has to be connected to both vdd_core pins and to the vdd_mem, vdd_padsa, vdd_vco, vdd_rf, vdd_if, vdd_pre and vdd_synth pins. 6 -2 120 - 035x - 000 rev. 1.2 final
EM351 / em357 6.2 resets the em35x resets are generated from a number of sources. each of these reset sourc es feeds into central reset detection logic that causes various parts of the system to be reset depending on the state of the system and the nature of the reset event. 6.2.1 reset sources 6.2.1.1 power - on - resets (por hv and por lv) the em35x measures the voltage levels supplied to the three power domains. if a supply voltage drops below a low threshold, then a reset is applied. the reset is released if the supply voltage rises above a high threshold. there are three detection circuits for power - on - reset as follows: ? por h v monitors the always - on domain supply voltage. thresholds are given in table 6 - 1 . ? por lv core monitors the core domain supply voltage. thresholds are given in table 6 - 2 . ? por lv mem monitors the memory supply voltage. thresholds are given in table 6 - 3 . table 6 - 1 . por hv thresholds parameter test conditions min typ max unit always - on domain release 0.62 0.95 1.20 v always - on domain assert 0.45 0.65 0.85 v supply rise time from 0.5 v to 1.7 v 250 s table 6 - 2 . por lvcore thresholds parameter test conditions min typ m a x unit 1.25 v domain release 0.9 1.0 1.1 v 1.25 v domain assert 0.8 0.9 1.0 v table 6 - 3 por lvmem thresholds parameter test conditions min typ max unit 1.8 v domain release 1.35 1.5 1.65 v 1.8 v domain assert 1.26 1.4 1.54 v the por lvcore and por lvmem reset sources are merged to provide a single reset source, por lv, to the reset generation module, since the detection of either event needs to reset the same system modules. 6 -3 120 - 035x - 000 rev. 1.2 final
EM351 / em357 6.2.1.2 nreset pin a single active low pin, nreset, is provided to reset the system. thi s pin has a schmitt triggered input. to afford good noise immunity and resistance to switch bounce, the pin is filtered with the reset filter module and generates the pin reset source, nreset, to the reset generation module. table 6 - 4 contains the specification for the filter. table 6 - 4 . reset filter specification for nreset parameter min typ max unit reset filter time constant 2.1 12.0 16.0 s reset pulse width to guarantee a reset 26.0 s reset pulse width guaranteed not to cause a reset 0 1.0 s 6.2.1.3 watchdog reset the em35x contains a watchdog timer (see also the watchdog timer section) that is clocked by the internal 1 khz timing reference. when the timer expires it generates the reset source watchdog_reset to the reset generation module. 6.2.1.4 software reset the arm ? co rtex tm - m3 cpu can initiate a reset under software control. this is indicated with the reset source sysresetreq to the reset generation module. 6.2.1.5 option byte error the flash memory controller contains a state machine that reads configuration information from the information blocks in the flash at system start time. an error check is performed on the option bytes that are read from flash and, if the check fails, an error is signaled that provides the reset source opt_byte_error to the reset generation module. i f an option byte error is detected, the system restarts and the read and check process is repeated. if the error is detected again the process is repeated but stops on the 3 rd failure. the system is then placed into an emulated deep sleep where recovery is possible. in this state, flash memory readout protection is forced active to prevent secure applications from being compromised. 6.2.1.6 debug reset the serial wire/jtag interface (swj) provides access to the swj debug port (swj - dp) registers. by setting the regi ster bit cdbgrstreq in the swj - dp, the reset source cdbgrstreq is provided to the reset generation module. 6.2.1.7 jrst one of the em35x?s pins can function as the jtag reset, conforming to the requirements of the jtag standard. this input acts independently of al l other reset sources and, when asserted, does not reset any on - chip hardware except for the jtag tap. if the em35x is in the serial wire mode or if the swj is disabled, this input has no effect. 6 -4 120 - 035x - 000 rev. 1.2 final
EM351 / em357 6.2.1.8 deep sleep reset the power management module informs the res et generation module of entry into and exit from the deep sleep states. the deep sleep reset is applied in the following states: before entry into deep sleep, while removing power from the memory and core domain, while in deep sleep, while waking from deep sleep, and while reapplying power until reliable power levels have been detect by por lv. the power management module allows a special emulated deep sleep state that retains memory and core domain power while in deep sleep. 6.2.2 reset recording the em35x recor ds the last reset condition that generated a restart to the system. the reset conditions recorded are: ? por hv always - on domain power supply failure ? por lv core domain (por lvcore) or memory domain (por lvmem) power supply failure ? nreset pin reset assert ed ? watchdog watchdog timer expired ? sysresetreq software reset by sysersetreq from arm ? cortex tm - m3 cpu ? deep sleep wakeup wake - up from deep sleep ? option byte error error check failed when reading option bytes from flash note: while cpu lockup is shown as a res et condition in software, cpu lockup is not specifically a reset event. cpu lockup is set to indicate that the cpu entered an unrecoverable exception. execution stops but a reset is not applied. this is so that a debugger can interpret the cause of the err or. silicon labs recommends that in a live application (in other words, no debugger attached) the watchdog be enabled by default so that the em35x can be restarted. 6.2.3 reset generation module the reset generation module responds to reset sources and generates the following reset signals : ? poreset reset of the arm ? cortex tm - m3 cpu and arm ? cortex tm - m3 system debug components ( flash patch and breakpoint, data watchpoint and trace, instrumentation trace macrocell, nested vectored interrupt controller ). arm defines poreset as the region that is reset when power is applied. ? sysreset reset of the arm ? cortex tm - m3 cpu without resetting the core debug and system debug components , so that a live system can be reset without disturbing the debug configuration. ? dapreset res et to the swj?s ahb access port (ahb - ap) ? preset hv peripheral reset for always - on power domain, for peripherals that are required to retain their configuration across a deep sleep cycle ? preset lv peripheral reset for core power domain, for peripherals that a re not required to retain their configuration across a deep sleep cycle 6 -5 120 - 035x - 000 rev. 1.2 final
EM351 / em357 table 6 - 5 shows which reset sources generate certain resets. table 6 - 5 . generated resets reset source reset generation module output poreset sysreset dapreset preset hv preset lv por hv x x x x x por lv (due to waking from normal deep sleep) x x x x por lv ( not due to waking from normal deep sleep) x x x x x nreset x x x x watchdog x x x sysresetreq x x x option byte error x x x normal deep sleep x x x x emulated deep sleep x x debug reset x 6.3 clocks the em35x integrates four oscillators: ? 12 mhz rc oscillator ? 24 mhz crystal oscillator ? 10 khz rc oscillator ? 32.768 khz crystal oscillator figure 6 - 2 shows a block diagram of the clocks in the em35x. this simplified view shows all the clock so urces and the general areas of the chip to which they are routed. 6 -6 120 - 035x - 000 rev. 1.2 final
EM351 / em357 figure 6 - 2 . clocks block diagram pclk osc 32 k bus produces 6 mhz or 1 mhz sysclk oscrc clk 1 k oscillator fa il over monitor ( selects rc when xtal fails ) oschf osc 24 m fclk cpu bus ram ctrl ram bus bus flitf flash osc 24 m _ ctrl [ 0 ] osc 24 m _ ctrl [ 1 ] cpu _ clksel [ 0 ] st _ csr [ 2 ] sleeptmr _ cfg [ 0 ] sleeptmr _ cfg [ 7 : 4 ] debug _ emcr [ 24 ] adc _ cfg [ 2 ] timx _ smcr [ 2 : 0 ] timx _ or [ 1 : 0 ] timxclk digital in 12 mhz rc 24 mhz xtal 10 khz rc 32 khz digital in / 2 / 2 /( 2 ^ n ) oscillator sleeptmr _ clken [ 0 ] 32 khz xtal mac timer counter scx rategen systick counter timx counter adc sigmadelta sleep timer counter watchdog counter and traceclk digital out scxsclk digital i / o / n ( nominal 10 ) 6 -7 120 - 035x - 000 rev. 1.2 final
EM351 / em357 6.3.1 high - frequency internal rc oscillator (oschf) the high - frequency rc oscillator (oschf) is used as the default system clock source when power is applied to the core domain. the nominal frequency coming out of reset is 12 mhz and ember software calibrates this clock to 12 mhz. tabl e 6 - 6 contains the specification for the high frequency rc oscillator. most peripherals, excluding the radio peripheral, are fully functional using the oschf clock source. application softw are must be aware that peripherals are clocked at different speeds depending on whether oschf or osc24m is being used. since the frequency step of oschf is 0.3 mhz and the high - frequency crystal oscillator is used for calibration, the calibrated accuracy o f oschf is 1 50 khz 4 0 ppm . the uart and adc peripherals may not be usable due to the lower accuracy of the oschf frequency. table 6 - 6 . high - frequency rc oscillator specification parameter test conditions min typ max unit frequency at reset 6 12 20 mhz frequency steps 0.3 mhz duty cycle 40 60 % supply dependence change in supply = 0.1 v test at supply changes: 1.8 v to 1.7 v 5 % 6.3.2 high - frequency crystal oscillator (osc24m) the high - frequency crystal oscillator (osc24m) requires an external 24 mhz crystal with an accuracy of 40 ppm. based upon the application?s bill of materials and current consumption requirements, the external crystal may cover a range of esr requirements. table 6 - 7 contains the specification for the high frequency crystal oscillator. the crystal oscillator has a software - programmable bias circuit to minimize current consumption. ember software configures the bias circuit for minimum current consumption. all peripherals including the radio peripheral are fully functional using the osc24m clock source. application software must be aware that peripherals are clocked at d ifferent speeds depending on whether oschf or osc24m is being used. if the 24 mhz crystal fails, a hardware failover mechanism forces the system to switch back to the high - frequency rc oscillator as the main clock source, and a non - maskable interrupt (nmi) is signaled to the arm ? cortex tm - m3 nvic. table 6 - 7 . high - frequency crystal oscillator specification parameter test conditions min typ max unit frequency 24 mhz accuracy - 40 +40 ppm duty cycle 40 60 % start - up time at max bias 1 ms start up time at optimal bias 2 ms current consumption 200 300 a 6 -8 120 - 035x - 000 rev. 1.2 final
EM351 / em357 parameter test conditions min typ max unit current consumption at max bias 1 ma crystal with high esr 100 load capacitance 10 pf crystal capacitance 7 pf crystal power dissipation 200 w crystal with low esr 60 load capacitance 18 pf crystal capacitance 7 pf crystal power dissipation 1 mw 6.3.3 low - frequency internal rc oscillator (oscrc) a low - frequency rc oscillator (oscrc) is provided as an internal timing reference. the nominal frequency coming out of reset is 10 khz, and ember software calibrates this clock to 10 khz. from the tuned 10 khz oscillator (oscrc) ember software calibrates a fractional - n divider to produce a 1 khz reference clock, clk1k. table 6 - 8 contains the specification for the low frequency rc oscillator. table 6 - 8 . low - frequency rc oscillator specification parameter test conditions min typ max unit nominal frequency after trimming 9 10 11 khz analog trim step size 0.5 khz supply dependence for a voltage drop from 3.6 v to 3.1 v or 2.6 v to 2.1 v (without re - calibration) 1 % temperature dependence frequency variation with temperature for a change from - 40 o c to +85 o c (without re - calibration) 2 % 6.3.4 low - frequency crystal oscillator (osc32k) a low - frequency 32.768 khz crystal oscillator (osc32k) is provided as an optional timing reference for on - chip timers. this oscillator is designed for use with an external watch crystal. when using the 32.768 khz crystal, you must connect it to gpio pc6 and pc7, and must configure t hese two gpios for analog input. alternatively, when pc7 is configured as a digital input, pc7 can accept an external digital clock input instead of a 32.786 khz crystal. the digital clock input signal must be a 1 v peak - to - peak sine wave with a dc bias of 0.5 v. refer to chapter 7, gpio f or gpio configuration details. using the low - frequency oscillator, crystal or digital clock, is enabled through ember software. 6 -9 120 - 035x - 000 rev. 1.2 final
EM351 / em357 table 6 - 9 contains the specification for the low frequency crystal oscillator. table 6 - 9 . low - frequency crystal oscillator specification parameter test conditions min typ max unit frequency 32.768 khz accuracy at 25o c - 20 + 20 ppm load capacitance osc32a 27 pf load capacitance osc32b 18 pf crystal esr 100 k start - up time 2 s current consumption at 25c, vdd_pads=3.0 v 0.5 a 6.3.5 clock switching the em35x has two switching mechanisms for the main system clock, providing four clock modes. table 6 - 10 shows these clock modes and how they affect the internal cloc ks. the register bit osc24m_ctrl_osc24m_sel in the osc24m_ctrl register switches between the high - frequency rc oscillator (oschf) and the high - frequency crystal oscillator (osc24m) as the main system clock (sysclk). the peripheral clock (pclk) is always half the frequency of sysclk. the register bit cpu_clksel _field in the cpu_clksel register switches between pclk and sysclk to produce the arm ? cortex tm - m3 cpu clock (fclk). the default and preferred mode of operation is to run the cpu at the higher pclk frequency, 24 mhz, to give higher processing performance for all applications and improved duty cycling for applications usi ng sleep modes. in addition to these modes, further automatic control is invoked by hardware when flash programming is enabled. to ensure accuracy of the flash controller?s timers, the fclk frequency is forced to 12 mhz during flash programming and erase o perations. table 6 - 10 . system clock modes osc24m_ctrl_ osc24m_sel cpu_clksel_fi eld sysclk pclk fclk flash program/erase inactive flash program/erase active 0 (oschf) 0 (normal cpu) 12 mhz 6 mhz 6 mhz 12 mhz 0 (oschf) 1 (fast cpu) 12 mhz 6 mhz 12 mhz 12 mhz 1 (osc24m) 0 (normal cpu) 24 mhz 12 mhz 12 mhz 12 mhz 1 (osc24m) 1 (fast cpu) 24 mhz 12 mhz 24 mhz 12 mhz 6 -10 120 - 035x - 000 rev. 1.2 final
EM351 / em357 6.4 system timers 6.4.1 watchdog timer the em35x integrates a watchdog timer which can be enabled to provide protection against software crashes and arm ? cortex tm - m3 cpu lockup. by default, it is disabled at power up of the always - on power domain. the watchdog timer uses the calibrated 1 khz clock (clk1k) as its reference and provides a nominal 2.048 s ti meout. a low water mark interrupt occurs at 1.792 s and triggers an nmi to the arm ? cortex tm - m3 nvic as an early warning. when the watchdog is enabled, the timer must be periodically reset before it expires. the watchdog timer is paused when the debugger h alts the arm ? cortex tm - m3. additionally, the ember software that implements deep sleep functionality disables the watchdog when entering deep sleep and restores the watchdog, if it was enabled, when exiting deep sleep. ember software provides an api for e nabling, resetting, and disabling the watchdog timer. 6.4.2 sleep timer the em35x integrates a 32 - bit timer dedicated to system timing and waking from sleep at specific times. the sleep timer can use either the calibrated 1 khz reference (clk1k), or the 32 khz c rystal clock (clk32k). the default clock source is the internal 1 khz clock. the sleep timer has a prescaler, a divider of the form 2^n, where n can be programmed from 1 to 2^15. this divider allows for very long periods of sleep to be timed. ember softwar e?s default configuration is to use the prescaler to always produce a 1024 hz sleep timer tick. the timer provides two compare outputs and wrap detection, all of which can be used to generate an interrupt or a wake up event. while it is possible to do so, by default the sleep timer is not paused when the debugger halts the arm ? cortex tm - m3. silicon labs does not advise pausing the sleep timer when the debugger halts the cpu. to save current during deep sleep, the low - frequency internal rc oscillator (oscrc ) can be turned off. if oscrc is turned off during deep sleep and a low - frequency 32.768 khz crystal oscillator is not being used, then the sleep timer will not operate during deep sleep and sleep timer wake events cannot be used to wake up the em35x. embe r software provides the system timer software api for interacting with the sleep timer as well as using the sleep timer and rc oscillator during deep sleep. note: because the system timer software module handles all interactions with the sleep timer, the module will return the correct value in all situations. in the situation where the chip performs a deep sleep that maintains the system time and is woken up from an external event (that is, not a sleep timer event), the deep sleep module in the ember software del ays until the next sleep timer clock tick (up to 1 ms) to guarantee that the sleep timer updates correctly. 6.4.3 event timer the systick timer is an arm ? standard system timer in the nvic. the systick timer can be clocked from either the fclk (the clock going i nto the cpu) or the sleep timer clock. fclk is either the sysclk or pclk as selected by cpu_clksel register (see the clock switching section). 6.5 power management the em 35x?s power management system is designed to achieve the lowest deep sleep current consumption possible while still providing flexible wakeup sources, timer activity, and debugger operation. the em35x has four main sleep modes: ? idle sleep: puts the cpu int o an idle state where execution is suspended until any interrupt occurs. all power domains remain fully powered and nothing is reset. 6 -11 120 - 035x - 000 rev. 1.2 final
EM351 / em357 ? deep sleep 1: the primary deep sleep state. in this state, the core power domain is fully powered down and the sleep timer is active. ? deep sleep 2: the same as deep sleep 1 except that the sleep timer is inactive to save power. in this mode the sleep timer cannot wake up the em35x. ? deep sleep 0 (also known as emulated deep sleep): the chip emulates a true deep sleep without p owering down the core domain. instead, the core domain remains powered and all peripherals except the system debug components (itm, dwt, fpb, nvic) are held in reset. the purpose of this sleep state is to allow em35x software to perform a deep sleep cycle while maintaining debug configuration such as breakpoints. csyspwrupreq, cdbgpwrupreq , and the corresponding csyspwrupack and cdbgpwrupack are bits in the debug port?s ctrl/stat register in the swj . for further information on these bits and the operation of the swj - dp please refer to the arm debug interface v5 architecture specification (arm ihi 0031a) . for further power savings when not in deep sleep, the adc, timer 1, timer 2, serial controller 1, and serial controller 2 peripherals can be individually d isabled through the peripheral_disable register. disabling a peripheral saves power by stopping the clock feeding that peripheral. a peripheral should only be disabled through the peripheral_disable register when the peripheral is idle and disabled through the peripheral's own configuration registers, otherwise undefined behavior may occur. when a peripheral is disabled through the peripheral_disable register, all registers associated with that peripheral ignore all subsequent writes , and subsequent reads return the value seen in the register at the moment the peripheral is disabled. 6.5.1 wake sources when in deep sleep the em35x can be returned to the running state in a number of ways, and the wake sources are split depending on deep sleep 1 or deep sleep 2. th e following wake sources are available in both deep sleep 1 and 2. ? wake on gpio activity: wake due to change of state on any gpio. ? wake on serial controller 1: wake due to a change of state on gpio pin pb2. ? wake on serial controller 2: wake due to a change of state on gpio pin pa2. ? wake on irqd: wake due to a change of state on irqd. since irqd can be configured to point to any gpio, this wake source is another means of waking on any gpio activity. ? wake on setting of cdbgpwrupreq: wake due to setting the cdbgpwrupreq bit in the debug port in the swj. ? wake on setting of csyspwrupreq: wake due to setting the csyspwrupreq bit in the debug port in the swj. the following sources are only available in deep sleep 1 since the sleep timer is not active in deep sle ep 2. ? wake on sleep timer compare a. ? wake on sleep timer compare b. ? wake on sleep timer wrap. the following source is only available in deep sleep 0 since the swj is required to write a memory mapped register to set this wake source and the swj only has a ccess to some registers in deep sleep 0. ? wake on write to the wake_core register bit. the wakeup recording module monitors all possible wakeup sources. more than one wakeup source may be recorded because events are continually being recorded (not just in deep - sleep) and another event may happen between the first wake event and when the em35x wakes up. 6 -12 120 - 035x - 000 rev. 1.2 final
EM351 / em357 6.5.2 basic sleep modes the power management state diagram in figure 6 - 3 s hows the basic operation of the power management controller. figure 6 - 3 . power management state diagram deep sleep emulated deep sleep pre -deep sleep running idle sleep cdbgpwrupreq set cdbgpwrupreq cleared deep sleep requested ( wfi instruction with sleep_deep=1 ) interrupt csyspwrupreq & inhibit cdbgpwrupreq=0 & csyspwrupreq=0 wake up event or csyspwrupreq set (resets the processor) wake up event ( resets the processor ) cdbgpwrupreq =1 & csyspwrupreq=0 sleep requested ( wfi instruction with sleep _ deep = 0 ) in normal operation an application may request one of two low power modes t hrough program execution: ? idle sleep is achieved by executing a wfi instruction while the sleepdeep bit in the cortex system control register (scs_scr) is clear. this puts the cpu into an idle state where execution is suspended until an interrupt occurs. t his is indicated by the state at the bottom of the diagram. power is maintained to the core logic of the em35x during the idle sleeping state. ? deep sleep is achieved by executing a wfi instruction with the sleepdeep bit in scs_scr set. this triggers the st ate transitions around the main loop of the diagram, resulting in powering down the em35x?s core logic, and leaving only the always - on domain powered. wake up is triggered when one of the pre - determined events occurs. if a deep sleep is requested the em3 5x first enters a pre - deep sleep state. this state prevents any section of the chip from being powered off or reset until the swj goes idle (by clearing csyspwrupreq). this pre - deep sleep state ensures debug operations are not interrupted. in the deep slee p state the em35x waits for a wake up event which will return it to the running state. in powering up the core logic the arm ? cortex tm - m3 is put through a reset cycle and ember software restores the stack and application state to the point where deep sleep was invoked. 6 -13 120 - 035x - 000 rev. 1.2 final
EM351 / em357 6.5.3 further options for deep sleep by default the low - frequency internal rc oscillator (oscrc) is running during deep sleep (known as deep sleep 1). to conserver power, oscrc can be turned of during deep sleep. this mode is known as deep sleep 2. since the oscrc is disabled, the sleep timer and watchdog timer do not function and cannot wake the chip unless the low - frequency 32.768 khz crystal oscillator is used. non - timer based wake sources continue to function. once a wake event does occur, oscrc is restarted and comes back up. 6.5.4 use of debugger with sleep modes the debugger communicates with the em35x using the swj. when the debugger is logically connected, the cdbgpwrupreq bit in the debug port in the swj is set, and the em35x will only enter deep sleep 0 (the emulated deep sleep state). the cdbgpwrupreq bit indicates that a debug tool is logically connected to the chip and therefore debug state may be in the system debug components. to maintain the debug state in the system debug components only d eep sleep 0 may be used, since deep sleep 0 will not cause a power cycle or reset of the core domain. the csyspwrupreq bit in the debug port in the swj indicates that a debugger wants to access memory actively in the em35x. therefore, whenever the csyspwru preq bit is set while the em35x is awake, the em35x cannot enter deep sleep until this bit is cleared. this ensures the em35x does not disrupt debug communication into memory. clearing both csyspwrupreq and cdbgpwrupreq allows the em35x to achieve a true d eep sleep state (deep sleep 1 or 2). both of these signals also operate as wake sources, so that when a debugger logically connects to the em35x and begins accessing the chip, the em35x automatically comes out of deep sleep. when the debugger initiates acc ess while the em35x is in deep sleep, the swj intelligently holds off the debugger for a brief period of time until the em35x is properly powered and ready. note: the swj - dp signals csyspwrupreq and cdbgpwrupreq are only reset by a power - on - reset or a debugger. physically connecting or disconnecting a debugger from the chip will not alter the state of these signals. a debugger must logically communicate with the swj - dp to set or clear these two signals. for more information regarding the swj and the interaction o f debuggers with deep sleep, contact customer support for application notes and arm ? coresight tm documentation. 6 -14 120 - 035x - 000 rev. 1.2 final
EM351 / em357 6.5.5 registers peripheral_disable peripheral disable register address: 0x40004038 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 peridis_rsvd peridis_adc peridis_tim2 peridis_tim1 peridis_sc1 peridis_sc2 bitname bitfield access description peridis_rsvd [5] rw reserved: this bit can change during normal operation. when writing to peripheral_disable, the value of this bit must be preserved. peridis_adc [4] rw disable the clock to the adc peripheral. peridis_tim2 [3] rw disable the clock to the tim2 peripheral. peridis_tim1 [2] rw disable the clock to the tim1 peripheral. peridis_sc1 [1] rw disable the clock to the sc1 peripheral. peridis_sc2 [0] rw disable the clock to the sc2 peripheral. 6.6 security accelerator the em35x contains a hardware aes encryption engine accessible from the arm ? cortex tm - m3. nist - based ccm, ccm*, cbc - mac, and ctr modes are implemented in hardware. these modes are described in the ieee 802.15.4 - 2003 specification, with the exception of ccm*, which is described in the zigbee security services specification 1.0. 6 -15 120 - 035x - 000 rev. 1.2 final
EM351 / em357 7 gpio (general p urpose input / ou t put) the em35x has 24 multi - purpose gpio pins , which may be individually co nfigured as : ? g eneral purpose output ? general purpose open - drain output ? a lternate output controlled by a peripheral device ? a lternate open - drain output controlled by a peripheral device ? analog ? general purpose input ? general purpose input with pull - up or pull - down resistor the basic structure of a single gpio is illustrated in figure 7 - 1 . figure 7 - 1 . gpio block diagram gpio _ pxin gpio _ pxout gpio _ pxset gpio _ pxclr gpio _ pxwake gpio _ pxcfgh / l alternate output analog functions wake detection pin alternate input vdd _ pads gnd vdd _ pads gnd output control ( push pull , open drain , or disabled ) schmitt trigger vdd _ pads gnd protection diode protection diode p - mos n - mos a schmitt trigger converts the gpio pin voltage to a digital input value. th e digi tal input signal is then always routed to the gpio_ px in regis ter ; to the alt ernate inputs of associated perip heral device s; to wake detection logic if wake detection is enabled ; and , for certain pins, to interrupt generation logic. configuring a pin in analog mode disconnects the digital input from the pin and applies a high logic level to the input of the schmitt trigger. only one device at a time can control a gpio output . the output is controlled i n normal output mode by the gpio_ px out register and in alternate output mode by a peripheral device. when in input mode or analog mode, digital output is disabled . 7.1 gpio ports the 24 gpio pi ns are grouped into three ports: pa, pb , and pc. individual gpios within a port are numbered 0 to 7 according to thei r bit positions within the gpio registers. note: because gpio port registers ? function s are identical, the notation px is used here to refer to pa, pb, or pc. for example, gpio_pxin refers to the registers gpio_pain, gpio_pbin, and gpio_pcin. 7 -1 120 - 035x - 000 rev. 1.2 final
EM351 / em357 each of the three gpio ports has the following registers whose low - order eight bits correspond to the port?s eight gpio pins: ? gpio_ px in (input data register) returns the pin level (unless in analog mode) . ? gpio_ px out (output data register) controls the outp ut level in normal output mode . ? gpio_ px clr (clear output data register) clears bits in gpio_ px out . ? gpio_ px set (set output data register) sets bits in gpio_ px out . ? gpio_ px wake (wake monitor register) specifies the pins that can wake the em35x . in addition to these registers, each port has a pair of configuration registers, gpio_ px cfgh and gpio_ px cfgl. the se registers specify the basic operating mode for the port? s pins . gpio_ px cfgl configures the pins px [3:0] and gpio_ px cfgh configures the pins px [7:4] . for b revity, the notation gpio_ px cfgh/l refers to the pair of configuration registers. five gpio pins (pa6, pa7, pb6, pb7 and pc0 ) can sink and source higher current than standard gpio outputs. refer to table 2 - 5, digital i/o s pecifications in chapter 2, electrical characteristics, for more information. 7.2 configuration each pin has a 4 - bit configuration value in the gpio_pxcfgh/l register. the various gpio modes and the ir 4 - bit configuration value s are shown in table 7 - 1 . table 7 - 1 . gpio configuration modes gpio mode gpio_ px cfg h/l description analog 0x0 analog input or output. when in analog mode, t he digital input ( gpio_ px in ) always reads 1. input (floating) 0x4 digital input without an internal pull up or pull down. output is disabled . input ( pull - up or pull - down ) 0x8 digital input with a n internal pull up or pull down . a set bit in gpio_ px out selects pull up and a cleared bit selects pull down . output is disabled. output (push - pull) 0x1 push - pull output. gpio_ px out controls the output. output ( open - drain ) 0x5 open - drain output. gpio_ px out controls the output. if a pull up is required, it must be external. alternate output (push - pull) 0x9 push - pull output. an onboard peripheral controls the output. alternate output ( open - drain ) 0xd open - drain output. an onboard peripheral controls the output. if a pull up is required, it must be external. if a gpio ha s two peripheral s that can be the source of altern ate output m ode data, then other registers in addition to gpio_ px cfgh/l determine which peripheral controls the output . several gpios share an alternate output with timer 2 and the s erial c ontroller s . bits in timer 2?s tim2_or register control routing timer 2 outputs to different gpio s . bits in timer 2?s tim2_ccer register enable timer 2 outputs . w hen timer 2 outputs are enabled they override serial control ler output s . table 7 - 2 indicates the gpio mapping for timer 2 outputs depending on the bits in the register tim2_or . refer to chapter 9 , general purpose timers for complete information on timer configuration. 7 -2 120 - 035x - 000 rev. 1.2 final
EM351 / em357 table 7 - 2 . timer 2 output configuration controls timer 2 output option register bit gpio mapping s elected by tim2_or bit 0 1 tim2c1 tim2_or[4] pa0 pb1 tim2c2 tim2_or[5] pa3 pb2 tim2c3 tim2_or[6] pa1 pb3 tim2c4 tim2_or[7] pa2 pb4 for outputs assigned to the serial controllers, the serial interface mode registers ( sc x _mode ) determine how the gpio pin s are used. the alternate outputs of pa4 and pa5 can either provide packet trace data ( pti_en and pti_data ) , or synchronous cpu trace data ( tracedata2 and tracedata3 ) . the selection of packet trace or cpu trace is made through the ember software. if a gpio does not have an associated peripheral in alternate output mode, its output is set to 0. 7.3 forced functions f or s ome gpi os t he g pio_ px cfgh/l configuration will be overridden. these functions are forced when the em35x is reset and remain forced until software overrides the forced functions. table 7 - 3 shows the gpios that have different functions forced on them regardless of the gpio_pxcfgh/l registers . table 7 - 3 . gpio forced functions gpio forced mode forced signal pa7 open - drain output reg_en pc0 input with pull up jrst pc2 push - pull output jtdo pc3 input with pull up jdti pc4 1 input with pull up jtms pc4 1 bidirectional (push - pull output or floating input) controlled by debugger interface swdio 1 the choice of pc4?s forced signal is controlled by an external debug tool. jtms is forced when the swj is in jtag mode and swdio is forced when the swj is in serial wire mode. pa7 is forced to be the regulator enable signal, reg_en. if an external regula tor is used and controlled through reg_en , pa7?s forced functionality must not be overridden . if an external regulator is not used, reg_en may be disabled and pa7 may be reclaimed as a normal gpio. disabling reg_en is done by clearing the bit gpio_extregen in the gpio_dbgcfg register. pc0, pc2, pc3, and pc4 are forced to be the serial wire and jtag (swj) interface. when the em35x resets, these four gpio s are force d to operate in jtag mode. switching the debug interface between jtag mode and serial wire mode can only be accomplished by the external debug tool and cannot be affected by software executing on the em35x. due to the fact that serial wire mode can only be invoked by an external debug tool 7 -3 120 - 035x - 000 rev. 1.2 final
EM351 / em357 and jtag mode is forced when the em35x resets, a designer must treat all four debug gpio s as working in unison even though the serial wire interface only uses one of the gpio, pc4. note: a n application must disable all debug swj debug functionality to reclaim any of the four gpi o s : pc0, pc2, pc3, and pc4. disabling swj debug functionality prevent s external debug tools from operating, including flash programming and high - level debug tools . disabling the swj debugger interface is a ccomplished by setting t he gpio_debug dis bit in the gpio_dbgcfg registe r . when this bit is set, all debugger - related pins (pc0, pc2, pc3, pc4) behave as standard gpio s . if the swj debugger interface is already active, the bit gpio_debugdis cannot be set. w hen gpio_debugdis is set, the swj debugger interface can be reclaimed by activating the swj while the em35x is held in reset. if the swj debugger interface is forced active in this manner, the bit gpio_forcedbg is set in the gpio_dbgstat register. the swj debugger interface is defined as active when the cdbgpwrupreq signal, a bit in the debug port?s crtl/stat register in the swj, is set high by an external debug tool. 7.4 reset a full chip reset is one due to power on (low or high voltage), the nreset pin, the watchdog , or the sysresetreq bit . a full chip reset affects the gpio configuration as follows: ? the gpio_ px cfgh/l configuration s of all pins are configured as floating inputs. ? the gpio_extregen bit is set in the gpio_dbgcfg register, which overrid es the normal configuration for pa7. ? the gpio_debug dis bit in the gpio_dbgcfg register is cleared, all owing serial wire/jtag access to override the normal configuration of pc0, pc2, pc3, and pc4. 7.5 boot configuration nbootmode is a special alternate function o f pa5 that is active only during a pin reset (nreset) or a power - on - reset of the always - powered domain (por hv ) . if nbootmode is asserted (pulled or driven low) when coming out of reset , the processor starts execut ing an embedded serial - link - only monitor i nstead of its normal program. while in reset and during the subsequent power - on - reset s tartup delay ( 512 oschf clocks ) , pa5 is automatically configured as an input with a pull - up resistor. a t the end of this time , the em35x samples nbootmode : a high level selects normal boot mode , and a low level selects the embedded monitor . figure 7 - 2 shows the timing parameters for invoking monitor mode from a pin (nre set) reset. because oschf is running uncalibrated during the reset sequence, the time for 512 oschf clocks may vary as indicated. figure 7 - 2 . n bootmode and nreset timing . . . nreset oschf . . . . . . nbootmode 26 sec min . . . . . . . . . 512 clocks; 26 sec min ? 85 sec max nbootmode sampled; fib monitor mode entered nbootmode sampled by fib monitor code 7 -4 120 - 035x - 000 rev. 1.2 final
EM351 / em357 timing fo r a power - on - reset is similar except that oschf does not begin oscillating until up to 70 sec after both core and hv supplies are valid. combined with the maximum 250 sec allowed for hv to r amp from 0.5 v to 1.7 v, an additional 320 sec may be added to the 512 oschf clocks until nbootmode is sampled. if the monitor mode is selected (nbootmode is low after 512 clocks), the fib monitor software begins execution. in order to filter out inadvertent jumps into the monitor , the fib monitor re - samples the nbootmode signal after a 3 ms delay. if the signal is still low, then the device stays in monitor mode. if the signal is high, then monitor mode is exited and the normal program begins execution. in summary, the nbootmode signal must be held low for 4 ms i n order to properly i nvoke the fib monitor . after nbootmode has been sampled, pa5 is configured as a floating input like the other gpio configurations . the gpio_ bootmode bit in the gpio_dbgstat register captures the state of nbootmode so that software may act on this signal if required. note: to avoid inadvertently asse rting nbootmode, pa5?s capacitive load may not exceed 250 pf. 7.6 gpio modes 7.6.1 analog mode analog mode enables analog functions, and disconnects a pin from the digital input and output logic . only the f ollowing gpio pins have analog functions: ? pa4, pa5, pb5, pb6, pb7 , and pc1 can be analog inputs to the adc. ? pb0 can be an external analog voltage reference in put to the adc , or it can output the internal analog voltage reference from the adc . the ember software selects an internal or external voltage refer ence . ? pc6 and pc7 can connect to a n optional 32. 768 k hz crystal . note: when an external timing source is required, a 32. 768 k hz crystal is commonly connected to pc6 and pc7. alternatively, when pc7 is conf i gured as a digital input , pc7 can accept a digital external clock input. when configured in analog mode: ? the output drivers are disabled . ? the internal pull - up and pull - down resistors are disabled. ? the schmitt trigger input is connected to a high logic level. ? reading gpio_ px in returns a constant 1. 7.6.2 input mode input mode is used both for general purpose input and for on - chip peripheral inputs. input floating mode disables the internal pul l - up and pull - down resistors, leaving the pin in a high - impedance state. input pull - up or pull - down mode enables either an internal pull - up or pull - down resistor based on the gpio_pxout register. setting a bit to 0 in gpio_pxout enables the pull - down and setting a bit to 1 enables the pull up. when configured in input mode: ? the output drivers are disabled . ? a n internal pull - up or pull - down resistor may be activated depending on gpio_ px cfg h/l and gpio_ px out. ? the schmitt trigger input is connected to the pin. ? reading gpio_ px in returns the input at the p in. ? the input is also available to on - chip peripheral s . 7 -5 120 - 035x - 000 rev. 1.2 final
EM351 / em357 7.6.3 output mode output mode provides a general purpose output under direct software control. regardless of whether an output is configured as push - pull or open - drain , the gpio?s bit in the gpio_ px out regi ster control s the output. the gpio_ px set and gpio_ px clr registers can atomically set and clear bits within gpio_ px out register . these set and clear registers simplif y software using the output port because they eliminate the need to disable interrupts to perform an atomic read - modify - write operation of gpio_pxout . when configured in output mode: ? the output drivers are enabled and are contro l led by the value written to gpio_ px o ut: ? in open - drain mode : 0 activates the n - mos current sink ; 1 tri - states the pin. ? in push - pull mode : 0 activates the n - mos current sink ; 1 activates the p - mos current source. ? the internal pull - up and pull - down resistors are disabled. ? the schmitt trigger input is connected to the pin. ? reading gpio_ px in returns the input at the pin. ? read ing gpio_ px out returns the last value written to the register. note: depending on configuration and usage, gpio_pxout and gpio_pxin may not have the same value. 7.6.4 alternate output mode in this mode, the output is controlled by an on - chip peripheral instead of gpio_ px out and may be configured as either push - pull or open - drain . m ost peripherals require a particular output type ? twi requires an open - drain driver, for example ? but since using a peripheral does not by itself configure a pin, the gpio_pxcfgh/l registers must be configured properly for a peripheral?s particular needs. as described in the configuration section , when more than one peripheral can be the source of output data, registers in addition to gpio_ px cfgh/l determine which to use . when configured in alternate output mode: ? the output drivers are enabled and are controlled by the output of an on - chip peripheral: ? in open - drain mode : 0 activates the n - mos cur rent sink ; 1 tri - states the pin. ? in push - pull mode : 0 activates the n - mos current sink ; 1 activates the p - mos current source. ? the internal pull - up and pull - down resistors are disabled. ? the schmitt trigger input is connected to the pin. ? reading gpio_ px in re turns the input to the pin. note: depending on configuration and usage, gpio_pxout and gpio_pxin may not have the same value. 7.7 wake monitoring the gpio_ px wake register s specify which gpios are monitored to wake the processor . if a gpio?s wake enable bit is set in gpio_ px wake, then a change in the logic value of that gpi o cause s the em35x to wake from deep sleep. the logic value s of all gpio s are captured by hardware upon entering sleep. if any gpio?s logic value changes while in sleep and that gpio?s gpio_pxwake bit is set, then the em35x wake s from deep sleep. ( there is no mechanism for selecting a specific rising - edge, falling - edge, or level on a gpio : a ny change in logic value trigger s a wake event. ) hardware records t he fact that gpio activity caus ed a wa ke event, but not which s pecific gpio was responsible. instead, the ember software reads the state of the gpio s on waking to determine this . the register gpio _wakefilt contains bits to enable digital filtering of the external wakeup event sources: the gpio pins, sc1 activity, sc2 activity , and irqd. the digital filter operates by taking samples based on the (nominal ) 10 khz rc oscillator. if three samples in a row all have the same logic value, and this sampled logic value is different from the logi c value seen upon entering sleep, the filter output s a wakeup event . 7 -6 120 - 035x - 000 rev. 1.2 final
EM351 / em357 in order to use gpio pins to wake the em35x from deep sleep , the gpio_wake bit in the wake_sel register must be set . waking up from gpio activity does not work with pins configured for an alog mode since the digital logic input is always set to 1 when in analog mode. refer to chapter 6, system modules, f or information on the em35x ?s power management and sleep modes. 7.8 external interrupts the em35x can use up to four external interrupt sources ( irqa, irqb , irqc , and irqd ) , each with its own top - level nvic interrupt vector . since these external interrupt sources connect to the standard gpio input path, an external in terrupt pin may simultaneously be used by a peripheral device or even configured as an output. analog mode is the only gpio configuration that is not compatible with us ing a pin as an external interrupt. e xternal interrupts have individual triggering and filtering options selected using the registers gpio_intcfga, gpio_intcfgb, gpio_i ntcfgc, and gpio_intcfgd . the bit field gpio_intmod of the gpio_intcfgx register enables irq x ?s second - level interrupt and selects the triggering mode: 0 is disabled; 1 for rising edge; 2 for falling edge; 3 for both edges; 4 for active high level; 5 for a ctive low level. the minimum width needed to latch an unfiltered external interrupt in both level - and edge - triggered mode is 80 ns. with the digital filter enabled (the gpio_intfilt bit in the gpio_intcfgx register is set) , the minimum width needed is 450 ns. the register int_gpioflag is the second - level interrupt flag register that indicates pending external interrupt s. writing 1 to a bit in the int_gpioflag register clears the flag while writing 0 has no effect . if the interrupt is level - triggered , the f lag bit is set again immediately after being cleared if its input is still in the active state. two of the four external interrupts, irqa and irqb, have fixed pin assignments . t he other two external interrupts , irqc and irqd, can use any gpio pin. the gpio _irqcsel and gpio_irqdsel registers speci fy the gpio pin s assigned to irqc and irqd, respectively. table 7 - 4 shows how the gpio_irqcsel and gpio_irqdsel register values select the gpio pin used for the external interrupt . table 7 - 4 . irqc/ d gpio selection gpio_irqxsel gpio gpio_irqxsel gpio gpio_irqxsel gpio 0 pa0 8 pb0 1 6 pc0 1 pa1 9 pb1 17 pc1 2 pa2 10 pb2 18 pc2 3 pa3 11 pb3 19 pc3 4 pa4 12 pb4 20 pc4 5 pa5 13 pb5 21 pc5 6 pa6 14 pb6 22 pc6 7 pa7 15 pb7 23 pc7 in some cases, it may be useful to assign irqc or irqd to an input also in use by a peripheral, for example to generate an interrupt from the slave select signal ( n ssel) in a n spi slave mode interface. refer to chapter 11, interrupt system , for further information regarding the em35x interrupt system. 7 -7 120 - 035x - 000 rev. 1.2 final
EM351 / em357 7.9 debug control and status two gpio r egisters are largely concerned with debugger funct ions. gpio_dbgcfg can disable debugger operation, but has other miscellaneous control bits as well. gpio_dbgstat, a read - only register, return s status related to debugger activity (gpio_forcedbg and gpio_sw en) , as well a flag (gpio_bootmode) indicating whe ther n b ootmode was asserted at the last power - on or nreset - based reset. 7.10 gpio signal assignment summary the gpio signal assignments are shown in table 7 - 5 . 7 -8 120 - 035x - 000 rev. 1.2 final
EM351 / em357 table 7 - 5 . gpio signal assig n ments gpio analog alternate output input output current drive pa0 tim2c1 1 , sc2mosi tim2c1 1 , sc2mosi standard pa1 tim2c3 1 , sc2miso, sc2sda tim2c3 1 , sc2miso, sc2sda standard pa2 tim2c4 1 , sc2s c lk, sc2scl tim2c4 1 , sc2sclk standard pa3 tim2c2 1 , traceclk tim2c2 1 , sc2nssel standard pa4 adc4 pti_en, tracedata2 standard pa5 adc5 pti_data, tracedata3 nbootmode 2 standard pa6 tim1c3 tim1c3 high pa7 tim1c4, reg_en 3 tim1c4 high pb0 vref traceclk tim1clk, tim2msk, irqa standard pb1 tim2c1 4 , sc1txd, sc1mosi, sc1miso, sc1sda tim2c1 4 , sc1sda standard pb2 tim2c2 4 , sc1sclk tim2c2 4 , sc1miso, sc1mosi, sc1scl, sc1rxd standard pb3 tim2c3 4 , sc1sclk tim2c3 4 , sc1sclk, sc1ncts standard pb4 tim2c4 4 , sc1nrts tim2c4 4 , sc1nssel standard pb5 adc0 tim2clk, tim1msk standard pb6 adc1 tim1c1 tim1c1, irqb high pb7 adc2 tim1c2 tim1c2 high pc0 tracedata1 jrst 5 high pc1 adc3 tracedata0, swo standard pc2 jtdo 6 , swo standard pc3 jtdi 5 standard pc4 swdio 7 swdio 7 , jtms 7 standard pc5 tx_active standard pc6 osc32b ntx_active standard pc7 osc32a osc32_ext standard 1 default signal assignment (not remapped). 2 overrides during reset as an input with pull up. 3 overrides after reset as an open - drain output. 4 alternate signal assignment (remapped). 5 overrides in jtag mode as a input with pull up. 6 overrides in jtag mode as a push - pull output. 7 overrides in serial wire mode as either a push - pull output , or a floating input , controlled by the debugger. 7 -9 120 - 035x - 000 rev. 1.2 final
EM351 / em357 7.11 registers gpio_pxcfgl gpio_pacfgl port a configuration register (low) address: 0x4000b000 reset: 0x4444 gpio_pbcfgl port b con figuration register (low) address: 0x4000b400 reset: 0x4444 gpio_pccfgl port c configuration register (low) address: 0x4000b800 reset: 0x4444 substitute a, b, or c for x in the following detail description. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 px3_cfg px2_cfg 7 6 5 4 3 2 1 0 px1_cfg px0_cfg bitname bitfield access description px3_cfg [15:12] rw gpio configuration control. 0x0: analog, input or output (gpio_pxin always reads 1). 0x1: output, push - pull (gpio_pxout controls the output). 0x4: input, floating. 0x5: output, open - drain (gpio_pxout controls the output). 0x8: input, pulled up or down (selected by gpio_pxout: 0 = pull - down, 1 = pull - up). 0x9: alternate output, push - pull (p eripheral controls the output). 0xd: alternate output, open - drain (peripheral controls the output). px2_cfg [11:8] rw gpio configuration control: see px3_cfg above. px1_cfg [7:4] rw gpio configuration control: see px3_cfg above. px0_cfg [3:0] rw gpio configuration control: see px3_cfg above. 7 -10 120 - 035x - 000 rev. 1.2 final
EM351 / em357 gpio_pxcfgh gpio_pacfgh port a configuration register (high) address: 0x4000b004 reset: 0x4444 gpio_pbcfgh port b configuration register (high) address: 0x4000b404 reset: 0x4444 gpio_pccfgh port c configurati on register (high) address: 0x4000b804 reset: 0x4444 substitute a, b, or c for x in the following detail description. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 px7_cfg px6_cfg 7 6 5 4 3 2 1 0 px5_cfg px4_cfg bitname bitfield access description px7_cfg [15:12] rw gpio configuration control. 0x0: analog, input or output (gpio_pxin always reads 1). 0x1: output, push - pull (gpio_pxout controls the output). 0x4: input, floating. 0x5: output, open - drain (gpio_pxout controls the output). 0x8: input, pulled up or down (selected by gpio_pxout: 0 = pull - down, 1 = pull - up). 0x9: alternate output, push - pull (peripheral controls the output). 0xd: alternate output, open - drain (peripheral controls the output). px6_cfg [11:8] rw gpio configuration control: see px7_cfg above. px5_cfg [7:4] rw gpio configuration control: see px7_cfg above. px4_cfg [3:0] rw gpio configuration control: see px7_cfg above. 7 -11 120 - 035x - 000 rev. 1.2 final
EM351 / em357 gpio_pxin gpio_pain port a input data register address: 0x4000b008 reset: 0x0 gpio_pbin port b input data register address: 0x4000b408 reset: 0x0 gpio_pcin port c input data register address: 0x4000b808 reset: 0x0 substitute a, b, or c for x in the following detail description. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 px7 px6 px5 px4 px3 px2 px1 px0 bitname bitfield access description px7 [7] rw input level at pin px7. px6 [6] rw input level at pin px6. px5 [5] rw input level at pin px5. px4 [4] rw input level at pin px4. px3 [3] rw input level at pin px3. px2 [2] rw input level at pin px2. px1 [1] rw input level at pin px1. px0 [0] rw input level at pin px0. 7 -12 120 - 035x - 000 rev. 1.2 final
EM351 / em357 gpio_pxout gpio_paout port a output data register address: 0x4000b00c reset: 0x0 gpio_pbout port b output data register address: 0x4000b40c reset: 0x0 gpio_pcout port c output data register address: 0x4000b80c reset: 0x0 substitute a, b, or c for x in the following detail description. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 px7 px6 px5 px4 px3 px2 px1 px0 bitname bitfield access description px7 [7] rw output data for px7. px6 [6] rw output data for px6. px5 [5] rw output data for px5. px4 [4] rw output data for px4. px3 [3] rw output data for px3. px2 [2] rw output data for px2. px1 [1] rw output data for px1. px0 [0] rw output data for px0. 7 -13 120 - 035x - 000 rev. 1.2 final
EM351 / em357 gpio_pxclr gpio_paclr port a output clear register address: 0x4000b014 reset: 0x0 gpio_pbclr port b output clear register address: 0x4000b414 reset: 0x0 gpio_pcclr port c output clear register address: 0x4000b814 reset: 0x0 substitute a, b, or c for x in the following detail description. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 px7 px6 px5 px4 px3 px2 px1 px0 bitname bitfield access description px7 [7] w write 1 to clear the output data bit for px7 (writing 0 has no effect). px6 [6] w write 1 to clear the output data bit for px6 (writing 0 has no effect). px5 [5] w write 1 to clear the output data bit for px5 (writing 0 has no effect). px4 [4] w write 1 to clear the output data bit for px4 (writing 0 has no effect). px3 [3] w write 1 to clear the output data bit for px3 (writing 0 has no effect). px2 [2] w write 1 to clear the output data bit for px2 (wr iting 0 has no effect). px1 [1] w write 1 to clear the output data bit for px1 (writing 0 has no effect). px0 [0] w write 1 to clear the output data bit for px0 (writing 0 has no effect). 7 -14 120 - 035x - 000 rev. 1.2 final
EM351 / em357 gpio_pxset gpio_paset port a output set register address: 0x4000b010 reset: 0x0 gpio_pbset port b output set register address: 0x4000b410 reset: 0x0 gpio_pcset port c output set register address: 0x4000b810 reset: 0x0 substitute a, b, or c for x in the following detail description. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 gpio_pxsetrsvd 7 6 5 4 3 2 1 0 px7 px6 px5 px4 px3 px2 px1 px0 bitname bitfield access description gpio_pxsetrsvd [15:8] w reserved: these bits must be set to 0. px7 [7] w write 1 to set the output data bit for px7 (writing 0 has no effect). px6 [6] w write 1 to set the output data bit for px6 (writing 0 has no effect). px5 [5] w write 1 to set the output data bit for px5 (writing 0 has no effect). px4 [4] w write 1 to set the output data bit for px4 (writing 0 has no effect). px3 [3] w write 1 to set the output data bit for px3 (writing 0 has no effect). px2 [2] w write 1 to set the output data bit for px2 (writing 0 has no effect). px1 [1] w write 1 to set the output data bit for px1 (writing 0 has no effect). px0 [0] w write 1 to set the output data bit for px0 (writing 0 has no effect). 7 -15 120 - 035x - 000 rev. 1.2 final
EM351 / em357 gpio_pxwake gpio_pawake port a wakeup monitor register address: 0x4000bc08 reset: 0x0 gpio_pbwake port b wakeup monitor register address: 0x4000bc0c reset: 0x0 gpio_pcwake port c wakeup monitor register address: 0x4000bc10 reset: 0x0 substitute a, b, or c for x in the following detail description. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 px7 px6 px5 px4 px3 px2 px1 px0 bitname bitfield access description px7 [7] rw write 1 to enable wakeup monitoring of px7. px6 [6] rw write 1 to enable wakeup monitoring of px6. px5 [5] rw write 1 to enable wakeup monitoring of px5. px4 [4] rw write 1 to enable wakeup monitoring of px4. px3 [3] rw write 1 to enable wakeup monitoring of px3. px2 [2] rw write 1 to enable wakeup monitoring of px2. px1 [1] rw write 1 to enable wakeup monitoring of px1. px0 [0] rw write 1 to enable wakeup monitoring of px0. 7 -16 120 - 035x - 000 rev. 1.2 final
EM351 / em357 gpio_wakefilt gpio wakeup filtering register address: 0x4000bc1c reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 irq d _wak e _filte r sc2_wake_filter sc1_wake_filter gpio_wake_filter bitname bitfield access description irqd_wake_filter [3] rw enable filter on gpio wakeup source irqd. sc2_wake_filter [2] rw enable filter on gpio wakeup source sc2 (pa2). sc1_wake_filter [1] rw enable filter on gpio wakeup source sc1 (pb2). gpio_wake_filter [0] rw enable filter on gpio wakeup sources enabled by the gpio_pnwake registers. 7 -17 120 - 035x - 000 rev. 1.2 final
EM351 / em357 gpio_irqxsel gpio_irqcsel interrupt c select register address: 0x4000bc14 reset: 0xf gpio_irqdsel interrupt d select register address: 0x4000bc18 reset: 0x10 substitute c or d in the detailed description below. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 sel_gpio bitname bitfield access description sel_gpio [4:0] rw pin assigned to irqx. 0x00: pa0. 0x01: pa1. 0x02: pa2. 0x03: pa3. 0x04: pa4. 0x05: pa5. 0x06: pa6. 0x07: pa7. 0x08: pb0. 0x09: pb1. 0x0a: pb2. 0x0b: pb3. 0x0c: pb4. 0x0d: pb5. 0x0e: pb6. 0x0f: pb7. 0x10: pc0. 0x11: pc1. 0x12: pc2. 0x13: pc3. 0x14: pc4. 0x15: pc5. 0x16: pc6. 0x17: pc7. 0x18 - 0x1f: reserved. 7 -18 120 - 035x - 000 rev. 1.2 final
EM351 / em357 gpio_intcfgx gpio_intcfga gpio interrupt a configuration register address: 0x4000a860 reset: 0x0 gpio_intcfgb gpio interrupt b configuration register address: 0x4000a864 reset: 0x0 gpio_intcfgc gpio interrupt c configuration register address: 0x4000a868 reset: 0x0 gpio_intcfgd gpio interrupt d configuration register address: 0x4000a86c reset: 0x0 substitute a, b, c, or d for x in the following detail description. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 gpio_intfilt 7 6 5 4 3 2 1 0 gpio_intmod 0 0 0 0 0 bitname bitfield access description gpio_intfilt [8] rw set this bit to enable digital filtering on irqx. gpio_intmod [7:5] rw irqx triggering mode. 0x0: disabled. 0x1: rising edge triggered. 0x2: falling edge triggered. 0x3: rising and falling edge triggered. 0x4: active high level triggered. 0x5: active low level triggered. 0x6, 0x7: reserved. 7 -19 120 - 035x - 000 rev. 1.2 final
EM351 / em357 int_gpioflag gpio interrupt flag register address: 0x4000a814 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 int_irqdflag int_irqcflag int_irqbflag int_irqaflag bitname bitfield access description int_irqdflag [3] rw irqd interrupt pending. write 1 to clear irqd interrupt (writing 0 has no effect). int_irqcflag [2] rw irqc interrupt pending. write 1 to clear irqc interrupt (writing 0 has no effect). int_irqbflag [1] rw irqb interrupt pending. write 1 to clear irqb interrupt (writing 0 has no effect). int_irqaflag [0] rw irqa interrupt pending. write 1 to clear irqa interrupt (writing 0 has no effect). 7 -20 120 - 035x - 000 rev. 1.2 final
EM351 / em357 gpio_dbgcfg gpio debug configuration register address: 0x4000bc00 reset: 0x10 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 gpio_debugdis gpio_extregen gpio_dbgcfgrsvd 0 0 0 bitname bitfield access description gpio_debugdis [5] rw disable debug interface override of normal gpio configuration. 0: permit debug interface to be active. 1: disable debug interface (if it is not already active). gpio_extregen [4] rw enable reg_en override of pa7's normal gpio configuration. 0: disable override. 1: enable override. gpio_dbgcfgrsvd [3] rw reserved: this bit can change during normal operation. when writing to gpio_dbgcfg, the value of this bit must be preserved. 7 -21 120 - 035x - 000 rev. 1.2 final
EM351 / em357 gpio_dbgstat gpio debug status register address: 0x4000bc04 reset: 0x0 31 30 29 28 2 7 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 gpio_bootmode 0 gpio_forcedbg gpio_swen bitname bitfield access description gpio_bootmode [3] r the state of the nbootmode signal sampled at the end of reset. 0: nbootmode was not asserted (it read high). 1: nbootmode was asserted (it read low). gpio_forcedbg [1] r status of debugger interface. 0: debugger interface not forced active. 1: debugger interface forced active by debugger cable. gpio_swen [0] r status of serial wire interface. 0: not enabled by swj - d p. 1: enabled by swj - d p. 7 -22 120 - 035x - 000 rev. 1.2 final
EM351 / em357 8 serial controllers 8.1 overview the em35x has two serial controllers, sc1 and sc2, which provide several options for full - duplex synchronous and asynchronous serial communications. ? spi (serial peripheral interface) , master or slave ? twi (two wire serial interface) , master only ? uart (universal asynchronous receiver/transmitter), sc1 only ? r eceive and t ransmit fifos and dma channels, spi and uart modes r eceive and transmit fifos allow faste r data speeds using by te - at - a - time inter rupts. for the highest spi and uart speeds, dedicated receive and transmit dma channels reduce cpu loading and extend the allowable time to service a serial controller interrupt. p olled operation is also possible usi ng direct access to the serial data registers. figure 8 - 1 shows the components of the serial controllers. note: t he notation s cx means that either sc1 or sc2 may be substitu ted to form the name of a specific register or field with i n a register . figure 8 - 1 . serial controller block diagram sc 1 _ uartstat scx _ spistat scx _ spicfg scx _ twistat scx _ twictrl 1 scx _ twictrl 2 scx _ ratelin / exp sc 1 _ uartper / frac baud generator clock generator uart controller tw i master controller scx _ data spi master controller uar t spi twi off scx _ mode 0 1 2 3 n rts n cts s clk m osi miso sda txd rxd rx - fifo tx - fifo scx _ tx / rxbega / b scx _ rxcnta / b scx _ txcnt scx _ dmastat scx _ dmactrl scx _ rxerra / b dma controller scl int _ scxflag int _ scxcfg sc 1 _ uartcfg scx interrupt scx tx dma channel scx rx dma channel scx _ tx / rxenda / b spi slave controller nssel scx _ rxcntsaved sc 1 only 8 -1 120 - 035x - 000 rev. 1.2 final
EM351 / em357 8.2 configuration before using a serial controller, con figure and initialize it as follows: ? set up the parameters specific t o the operating mode (master/ slave for spi, baud rate for uart, etc.). ? configure the gpio pins u sed by the serial controller as shown in table 8 - 1 and table 8 - 2 . section 2 in chapter 7, gpio shows how to configure gpio pins. ? if u sing dma, set up the dma and buffers. this i s described fully in section 8.7 . ? if using interrupts, select edge - or level - triggered interrupts with the scx _intmode register , enable the desired second - lev el interrupt sources in the int_scxcfg register , and finally enable the top - level scx inter rupt in the nvic . ? write the serial interface operating mode ? spi, twi , or uart ? to the scx_mode register. table 8 - 1 . sc1 gpio usage and configuration pb 1 pb 2 pb 3 pb 4 spi - master sc1mosi alternate output ( push - pull ) sc1miso input sc1sclk alternate output ( push - pull ) (not used) spi - slave sc1miso alternate output ( push - pull ) sc1mosi input sc1sclk input sc1 n ssel input twi - master sc1sda alternate output ( open - drain ) sc1 scl alternate output ( open - drain ) (not used) (not used) uart txd alternate output ( push - pull ) rxd input ncts i nput 1 nrts alternate output ( push - pull ) 1 1 used if rts/cts hardware flow control is enabled. table 8 - 2 . sc2 gpio usage and configuration pa 0 pa 1 pa 2 pa 3 spi - master sc2mosi alternate output ( push - pull ) sc2miso input sc2sclk alternate output ( push - pull ) (not used) spi - slave sc2mosi input sc2miso alternate output (push - pull) sc2sclk input sc2 n ss el input twi - master (not used) sc2sda alternate output ( open - drain ) sc2scl alternate output ( open - drain ) (not used) 8 -2 120 - 035x - 000 rev. 1.2 final
EM351 / em357 8.2.1 registers scx_mode sc1_mode serial mode register address: 0x4000c854 reset: 0x0 sc2_mode serial mode register address: 0x4000c054 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 sc_mode bitname bitfield access description sc_mode [1:0] rw serial controller mode. 0: disabled. 1: uart mode (valid only for sc1). 2: spi mode. 3: twi mode. 8 -3 120 - 035x - 000 rev. 1.2 final
EM351 / em357 int_scxflag int_sc1flag serial controller 1 interrupt flag register address: 0x4000a808 reset: 0x0 int_sc2flag serial controller 2 interrupt flag register address: 0x4000a80c reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 int_sc1parerr int_sc1frmerr int_sctxuldb int_sctxulda int_scrxuldb int_scrxulda int_scnak 7 6 5 4 3 2 1 0 int_sccmdfin int_sctxfin int_scrxfin int_sctxund int_scrxovf int_sctxidle int_sctxfree i n t _s cr xva l bitname bitfield access description int_sc1parerr [14] rw parity error received (uart) interrupt pending. int_sc1frmerr [13] rw frame error received (uart) interrupt pending. int_sctxuldb [12] rw dma transmit buffer b unloaded interrupt pending. int_sctxulda [11] rw dma transmit buffer a unloaded interrupt pending. int_scrxuldb [10] rw dma receive buffer b unloaded interrupt pending. int_scrxulda [9] rw dma receive buffer a unloaded interrupt pending. int_scnak [8] rw nack received (twi) interrupt pending. int_sccmdfin [7] rw start/stop command complete (twi) interrupt pending. int_sctxfin [6] rw transmit operation complete (twi) interrupt pending. int_scrxfin [5] rw receive operation complete (twi) interrupt pending. int_sctxund [4] rw transmit buffer underrun interrupt pending. int_scrxovf [3] rw receive buffer overrun interrupt pending. int_sctxidle [2] rw transmitter idle interrupt pending. int_sctxfree [1] rw transmit buffer free interrupt pending. int_scrxval [0] rw receive buffer has data interrupt pending. 8 -4 120 - 035x - 000 rev. 1.2 final
EM351 / em357 int_scxcfg int_sc1cfg serial controller 1 interrupt configuration register address: 0x4000a848 reset: 0x0 int_sc2cfg serial controller 2 interrupt configuration register address: 0x4000a84c reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 int_sc1parerr int_sc1frmerr int_sctxuldb int_sctxulda int_scrxuldb int_scrxulda int_scnak 7 6 5 4 3 2 1 0 int_sccmdfin int_sctxfin int_scrxfin int_sctxund int_scrxovf int_sctxidle int_sctxfree i n t _s cr xva l bitname bitfield access description int_sc1parerr [14] rw parity error received (uart) interrupt enable. int_sc1frmerr [13] rw frame error received (uart) interrupt enable. int_sctxuldb [12] rw dma transmit buffer b unloaded interrupt enable. int_sctxulda [11] rw dma transmit buffer a unloaded interrupt enable. int_scrxuldb [10] rw dma receive buffer b unloaded interrupt enable. int_scrxulda [9] rw dma receive buffer a unloaded interrupt enable. int_scnak [8] rw nack received (twi) interrupt enable. int_sccmdfin [7] rw start/stop command complete (twi) interrupt enable. int_sctxfin [6] rw transmit operation complete (twi) interrupt enable. int_scrxfin [5] rw receive operation complete (twi) interrupt enable. int_sctxund [4] rw transmit buffer underrun interrupt enable. int_scrxovf [3] rw receive buffer overrun interrupt enable. int_sctxidle [2] rw transmitter idle interrupt enable. int_sctxfree [1] rw transmit buffer free interrupt enable. int_scrxval [0] rw receive buffer has data interrupt enable. 8 -5 120 - 035x - 000 rev. 1.2 final
EM351 / em357 scx_intmode sc1_intmode serial controller 1 interrupt mode register address: 0x4000a854 reset: 0x0 sc2_intmode serial controller 2 interrupt mode register address: 0x4000a858 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 sc_txidlelevel sc_txfreelevel sc_rxvallevel bitname bitfield access description sc_txidlelevel [2] rw transmitter idle interrupt mode - 0: edge triggered, 1: level triggered. sc_txfreelevel [1] rw transmit buffer free interrupt mode - 0: edge triggered, 1: level triggered. sc_rxvallevel [0] rw receive buffer has data interrupt mode - 0: edge triggered, 1: level triggered. 8.3 spi - master mode the spi master controller has the following features: ? full duplex operation ? programmable clock frequency ( 12 mhz max.) ? programmable clock polarity and phase ? selectable data shift direction (either lsb or msb first) ? r eceive and transmit fifos ? receive and transmit dma channels 8.3.1 gpio usage the spi master controller uses the three signals : ? mosi (master out, slave i n ) ? outputs serial data f rom the master ? miso (master in, slave out) ? inputs serial data from a slave ? sclk (serial clock) ? outputs the serial clock used by mosi and miso 8 -6 120 - 035x - 000 rev. 1.2 final
EM351 / em357 the gpio pins used for these signals are shown in table 8 - 3 . additional outputs may be needed to drive the nss el signals on slave devices. table 8 - 3 . spi master gpio usage mosi miso sclk direction output input output gpio configuration alternate output (push - pull) input alternate output ( push - pull ) sc1 pin pb 1 pb 2 pb 3 sc2 pin pa 0 pa 1 pa 2 8.3.2 set up and configuration both serial controllers, sc1 and sc2 , support spi master mode. spi master mode is enabled by the following register settings : ? t he serial controller mode register ( scx _mode ) is 2 . ? t he sc_spimst bit in the spi configuration register ( scx _spicfg ) is 1 . the spi serial clock ( sclk ) is produced by a programmable clock generator. the serial clock is produced by dividing down 12 mhz according to this equation: exp lin mhz rate 2 * ) 1 ( 12 + = 8 -7 120 - 035x - 000 rev. 1.2 final
EM351 / em357 table 8 - 4 . spi master mode formats scx_sp icfg frame format s sc_spixxx 1 mst ord pha pol 1 0 0 0 s clk out mo si out m iso in rx [ 7 ] tx [ 7 ] rx [ 6 ] tx [ 6 ] rx [ 5 ] tx [ 5 ] rx [ 4 ] tx [ 4 ] rx [ 3 ] tx [ 3 ] rx [ 2 ] tx [ 2 ] rx [ 1 ] tx [ 1 ] rx [ 0 ] tx [ 0 ] 1 0 0 1 mosi out miso in rx[7] tx[7] rx[6] tx[6] rx[5] tx[5] rx[4] tx[4] rx[3] tx[3] rx[2] tx[2] rx[1] tx[1] rx[0] tx[0] sclk out 1 0 1 0 mosi out miso in rx[7] tx[7] rx[6] tx[6] rx[5] tx[5] rx[4] tx[4] rx[3] tx[3] rx[2] tx[2] rx[1] tx[1] rx[0] tx[0] sclk out 1 0 1 1 mo si out m iso in rx [ 7 ] tx [ 7 ] rx [ 6 ] tx [ 6 ] rx [ 5 ] tx [ 5 ] rx [ 4 ] tx [ 4 ] rx [ 3 ] tx [ 3 ] rx [ 2 ] tx [ 2 ] rx [ 1 ] tx [ 1 ] rx [ 0 ] tx [ 0 ] s clk out 1 1 - - same as above except data is sent lsb first instead of msb first 1 the notation xxx means that the corresponding column header below is inserted to form the field name. 8.3.3 operation c haracters transmitted and received by the spi master controller are buffered in transmit and receive fifos that are both 4 entries deep . when software writes a character to the scx _data register , the character is pushed onto the transmit fifo . s imilarly, when software reads from the scx _data register , the character returned is pull ed from the receive fifo. if the transmit and receive d ma channels are used, they also write to and read from the transmit and receive fifos. when the transmit fifo and the serializer are both empty , writing a character to the transmit fifo clears the sc_spitxidle bit in the scx _spist at regis ter. this indicate s that some characters have not yet been transmit ted. if charac ters are written to the transmit fifo until it is full, the sc_spitxfree bit in the scx _spistat regi ster is clear ed . s hifting out a character to the mosi pin sets the sc_spitxfree bit in the scx _spistat register. when the transmit fifo empties and the l a st character has been shifted out , the sc_spitxidle bit in the scx _spistat register is set . c haracter s received are stored in the receive fifo. r eceiving character s sets the sc_spirxval bit in the scx _spistat register , indicating that character s can be read from the receive fifo. c haracters received while the receive f ifo is full are dropped , and the sc_spirxovf bit in the scx _spistat register is set. the receive fifo hardware generates the int_scrxovf interrupt, but the dma register will not indicate the error condition until the receive fifo is drained. once the dma marks a receive e rror, two conditions will clear the error indication: setting the appropriate sc _tx/rxdmarst bit in the scx _dmactrl register, or loading the appropriate dma buffer after it has unloaded. to receive a character, you must transmit a character. if a long stream of receive characters is expected, a long sequence of dummy transmit characte rs must be generated. to avoid software or transmit dma initiating these transfers and consuming unnecessary bandwidth, the spi serializer can be instructed to retransmit the 8 -8 120 - 035x - 000 rev. 1.2 final
EM351 / em357 last transmitted character or to transmit a busy token ( 0xff ), which is deter mine d by the sc_spirpt bit in the scx _spicfg register. this functionality can only be enabled or disabled when the transmit fifo is empty and the transmit serializer is idle, indicated by a cleared sc_spitxidle bit in the scx _spistat register. refer to the reg ister description of scx_spicfg for more detailed information about sc_spirpt . every time an automatic character transmission starts , a transmit underrun is detected as there is no data in transmit fifo , and the int_sctxund bit in the int_sc2flag register is set. a fter automatic character transmission is disabled , no more new characters are received. t he receive fifo holds characters just received. note: the receive dma complete event does not always mean the receive fifo is empty. the dma channels section describes how to configure and use the serial receive and transmit dma channels. 8.3.4 interrupts spi master controller second - level i nterrupts are generated by the following ev ents: ? transmit fifo empty and last characte r shifted out (depending on scx _intmode , either the 0 to 1 transition or the high level of sc_spitxidle ) ? transmit fifo changed from full to not full ( depending on scx _intmode , either the 0 to 1 transition or the h igh level of sc_spitxfree ) ? receive fifo changed from empty to not empty ( depending on scx _intmode , either the 0 to 1 transition or the high level of sc_spirxval ) ? transmit dma buffer a/b complete (1 to 0 transition of sc_txacta/b ) ? receive dma buffer a/b complete (1 to 0 transition of sc_rxacta/b ) ? received and lost character while r eceive fifo was full (r eceive overrun error) ? transmitted character while t ransmit fifo was empty (t ransmit underrun error) to enable cpu interrupts, set the desired interrupt bits in the second - level int_ scx cfg register, and enable the top - level scx interrupt in the nvic by writing the int_ scx bit in the int_cfgset register. 8 -9 120 - 035x - 000 rev. 1.2 final
EM351 / em357 8.3.5 registers scx_data sc 1 _d ata serial data register address: 0x4000c83c reset: 0x0 sc 2 _d ata serial data register address: 0x4000c03c reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 s c_ d ata bitname bitfield access description s c _data [7:0] rw transmit and receive data register. writing to this register adds a byte to the transmit fifo. reading from this register takes the next byte from the receive fifo and clears the overrun error bit if it was set. in uart mode (sc1 only), reading from this r egister loads the uart status register with the parity and frame error status of the next byte in the fifo, and clears these bits if the fifo is now empty. 8 -10 120 - 035x - 000 rev. 1.2 final
EM351 / em357 scx_spicfg sc1_spicfg spi configuration register address: 0x4000c858 reset: 0x0 sc2_spicfg spi configuration register address: 0x4000c058 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 sc_spirxdrv sc_spimst sc_spirpt sc_spiord sc_spipha sc_spipol bitname bitfield access description sc_spirxdrv [5] rw receiver - driven mode selection bit (spi master mode only). clear this bit to initiate transactions when transmit data is available. set this bit to initiate transactions when the receive buffer (fifo or dma) has space. sc_spimst [4] rw set this bit to put the spi in master mode, clear this bit to put the spi in slave mode. sc_spirpt [3] rw this bit controls behavior when the transmit serializer must send a byte and there is no data already available in /to the serializer. the conditions for send ing this ?busy? token are transmit buffer underrun condition when using dma in master or slave mode, empty fifo in slave mode, and the busy token will alw ays be sent as the first byte every time nssel is asserted while operating in slave mode. clear this bit to send the busy token (0xff) and set this bit to repeat the last byte. changes to this bit take effect when the transmit fifo is empty and the transmi t serializer is idle. note that when the chip comes out of reset, if sc_spirpt is set before any data has been transmitted and no data is available (in the fifo), the ?last byte? that will be transmitted after the padding byte is 0x00 due to the fifo havin g been reset to 0x00. sc_spiord [2] rw this bit specifies the bit order in which spi data is transmitted and received. 0: most significant bit first. 1: least significant bit first. sc_spipha [1] rw clock phase configuration: clear this bit to sample on the leading (first edge) and set this bit to sample on the second edge. sc_spipol [0] rw clock polarity configuration: clear this bit for a rising leading edge and set this bit for a falling leading edge. 8 -11 120 - 035x - 000 rev. 1.2 final
EM351 / em357 scx_spistat sc1_spistat spi status register address: 0x4000c840 reset: 0x0 sc2_spistat spi status register address: 0x4000c040 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 sc_spitxidle sc_spitxfree sc_spirxval sc_spirxovf bitname bitfield access description sc_spitxidle [3] r this bit is set when both the transmit fifo and the transmit serializer are empty. sc_spitxfree [2] r this bit is set when the transmit fifo has space to accept at least one byte. sc_spirxval [1] r this bit is set when the receive fifo contains at least one byte. sc_spirxovf [0] r this bit is set if a byte is received when the receive fifo is full. this bit is cleared by reading the data register. 8 -12 120 - 035x - 000 rev. 1.2 final
EM351 / em357 scx_ratelin sc1_ratelin serial clock linear prescaler register address: 0x4000c860 reset: 0x0 sc2_ratelin serial clock linear prescaler register address: 0x4000c060 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 s c_ r at e l i n bitname bitfield access description sc_ratelin [3:0] rw the linear component (lin) of the clock rate in the equation: rate = 12mhz / ( (lin + 1) * (2^exp) ) 8 -13 120 - 035x - 000 rev. 1.2 final
EM351 / em357 scx_rateexp sc1_rateexp serial clock exponential prescaler register address: 0x4000c864 reset: 0x0 sc2_rateexp serial clock exponential prescaler register address: 0x4000c064 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 sc_rateexp bitname bitfield access description sc_rateexp [3:0] rw the exponential component (exp) of the clock rate in the equation: rate = 12mhz / ( (lin + 1) * (2^exp) ) 8.4 spi - slave mode both sc1 and sc2 spi controllers include a spi slave controller with the se features: ? full duplex operation ? u p to 5 mbps data transfer rate ? programmable clock polarity and clock phase ? selectable data shift direction (either lsb or msb first) ? s lave select input 8.4.1 gpio usage the spi slave controller uses four signals: ? mosi (master out, slave i n ) ? inputs serial data from the master ? miso (master in, slave out) ? outputs serial data to the master ? sclk (serial clock) ? clocks data transfers on mosi and miso ? nss el (slave select) ? enables serial communication with the slave note: the spi sl ave controller does not tri - state the miso signal when slave select is deasserted. 8 -14 120 - 035x - 000 rev. 1.2 final
EM351 / em357 the gpio pins that can be assigned to these signals are shown in table 8 - 5 . table 8 - 5 . spi slave gpio usage mosi miso sclk nss el direction input output input input gpio config uration input alternate output (push - pull) input input sc1 pin pb 2 pb 1 pb 3 pb 4 sc2 pin pa 0 pa 1 pa 2 pa 3 8.4.2 set up and configuration both serial controllers, sc1 and sc2, support spi slave mode. spi slave mode is enabled by the following register settings: ? t he serial controller mode register, scx _mode , is 2 ? t he sc_spimst bit in the spi configuration register, scx _spicfg , is 0 the spi slave c ontroller receives its clock from an external spi master device and supports rates up to 5 mbps. 8 -15 120 - 035x - 000 rev. 1.2 final
EM351 / em357 the spi slave controller supports various frame formats depending upon the clock polarity ( sc_spipol ), clock phase ( sc_spipha ), and direction of data ( sc_spiord ) (see table 8 - 6 ). the sc_spipol , sc_spipha , and sc_spiord bits are defined within the scx _spicfg registers. table 8 - 6 . spi slave formats scx _spicfg frame format sc_spixxx 1 mst ord pha pol 0 0 0 0 tx[7] rx[7] tx[6] rx[6] tx[5] rx[5] tx[4] rx[4] tx[3] rx[3] tx[2] rx[2] tx[1] rx[1] tx[0] rx[0] nssel sclk in mosi in miso out 0 0 0 1 tx[7] rx[7] tx[6] rx[6] tx[5] rx[5] tx[4] rx[4] tx[3] rx[3] tx[2] rx[2] tx[1] rx[1] tx[0] rx[0] sclk in mosi in miso out 0 0 1 0 tx[7] rx[7] tx[6] rx[6] tx[5] rx[5] tx[4] rx[4] tx[3] rx[3] tx[2] rx[2] tx[1] rx[1] tx[0] rx[0] nssel sclk in mosi in miso out 0 0 1 1 tx[7] rx[7] tx [ 6 ] rx [ 6 ] tx [ 5 ] rx [ 5 ] tx [ 4 ] rx [ 4 ] tx [ 3 ] rx [ 3 ] tx [ 2 ] rx [ 2 ] tx [ 1 ] rx [ 1 ] tx [ 0 ] rx [ 0 ] n ss el mosi in miso out sclk in 0 1 same as aove ecet ls first instead of ms first 1 the notation means that the corresonding column header elow is inserted to form the field name 8.4.3 operation when the slave select ( n ss el ) signal is asserted by the master , spi transmit data is driven to the output pin miso , and spi data is received from the input pin mosi. the nssel pin has to be asserted to enable the transmit serializer to drive data to the output signal miso. a falling edge on nss el reset s the spi slave shift registe r s . note: the spi slave controller does not tri - state the miso signal when slave select is deasserted. c haracters transmitted and received by the spi slave controller are buffered in the transmit and receive fifos that are both 4 entries deep . when software writ es a character to the scx _data register, it is pushed onto the transmit fifo. similarly, when software reads from the scx _data register, the character returned is pulled from the receive fifo. if the transmit and receive dma channels are used, the dma chan nels also write to and read from the transmit and receive fifos. c haracter s received are stored in the receive fifo. receiving characters sets the sc_spirxval bit in the scx _spistat register, to indicate that characters can be read from the receive fifo. characters received 8 -16 120 - 035x - 000 rev. 1.2 final
EM351 / em357 while the receive fifo is full are dropped , and the sc_spirxovf bit in the scx _spistat register is set. the receive fifo hardware generates the int_scrxovf interrupt, but the dma register will not indicate the error condition until the receive fifo is drained. once the dma marks a receive e rror, two conditions will clear the error indication: setting the appropriate sc_tx/rxdmarst bit in the scx _dmactrl register, or loading the appropriate dma buffer after it has unloaded. receiv ing a c haracter causes the serial transmission of a character pulled from the transmit fifo. when the transmit fifo is empty, a transmit underrun is detected (no data in transmit fifo) and the int_sctxund bit in the int_ scx flag register is set. because no charact er is available for serialization, the spi serializer retransmits the last transmitted character or a busy token ( 0xff ), determined by the sc_spirpt bit in the scx _spicfg register. refer to the register description of scx_spicfg for more detailed informati on about sc_spirpt. when the transmit fifo and the serializer are both empty , writing a character to the transmit fifo clears the sc_spitxidle bit in the scx _spistat regis ter. this indicates that not all characters have been transmit ted. if charac ters are written to the transmit fifo until it is full, the sc_spitxfree bit in the scx _spistat regi ster is clear ed . s hifting out a tran smit character to the m i so pin causes the sc_spitxfree bit in the scx _spistat register to get set. when the transmit fifo emptie s and the last character has been shifted out , the sc_spitxidle bit in the scx _spistat register is set . the spi slave controller must guarantee that there is time to move new transmit data from the transmit fifo into the hardware serializer. to provide suf ficient time, the spi slave controller inserts a byte of padding at the start of every new string of transmit data defined by every time nss el is asserted . this byte is inserted as if this byte was placed there by software. the value of the byte of padding is always 0xff . 8.4.4 dma the dma channels section describes how to configure and use the serial receive and transmit dma channels. when using the receive dma channel and nss el transitions to the high (deasserted) state, the active bu ffe r?s receive dma count register ( scx _rxcnta/b ) is saved in the scx _rxcntsaved register . scx _rxcntsaved is only written the first time nss el goes high after a buffer has been loaded . s ubsequent rising edges set a status bit but are otherwise ignored. the 3 - bit field sc_rxss el in the scx _dmastat register records what, if anything, was saved to the scx _rxcntsaved register, and whether or not a nother rising edge occurred on nss el . 8.4.5 interrupts spi slave controller second - level i nterrupts are g ener ated on the following events: ? transmit fifo empty and last character shifted out ( depending on scx _intmode , either the 0 to 1 transi tion or the high level of sc_spitxidle ) ? transmit fifo changed from full to not full ( depending on scx _intmode , either the 0 to 1 transi t ion or the high level of sc_spitxfree ) ? receive fifo changed from empty to not empty ( depending on scx _intmode , either the 0 to 1 transi tion or the high level of sc_spirxval ) ? transmit dma buffer a/b complete (1 to 0 transition of sc_txacta/b ) ? receive dma bu ffer a/b complete (1 to 0 transition of sc_rxacta/b ) ? received and lost character while r eceive fifo was full ( r eceive overrun error) ? transmitted character while t ransmit fifo was empty (t ransmit underrun error) to enable cpu interrupts , set desired interrupt bits i n the second - level int_ scx cfg register, and also enable the top - level scx interrupt in the nvic by writing the int_ scx bit in the int_cfgset register. 8 -17 120 - 035x - 000 rev. 1.2 final
EM351 / em357 8.4.6 registers refer to registers (in the spi master mode section) for a description of the scx _ data , scx_spicfg, and scx_spistat register s . 8.5 twi - two wire s erial interface s both em35x serial controllers sc1 and sc2 include a two wire serial interface (twi ) master controller with the following features: ? uses only two bidirectional gpio pins ? programma ble clock frequency (up to 400 khz ) ? supports both 7 - bit and 10 - bit addressing ? compatible with philips? i 2 c - b us slave devices 8.5.1 gpio usage the twi master controller uses just two signals: ? sda (serial data) ? bidirectional serial data ? scl (serial clock) ? bidirectional serial clock table 8 - 7 lists the gpio pins used by the sc1 and sc2 twi master controllers. because the pins are configured as open - drain outputs , they require externa l pull - up resistors . table 8 - 7 . twi master gpio usage sda scl direction input / output input / output gpio configuration alternate o utput (open drain) alternate output (open drain) sc1 pin pb 1 pb 2 sc2 pin pa 1 pa 2 8.5.2 set up and configuration the twi c ontroller is enabled by writing 3 to the scx _mode register. the twi controller operates only in master mode and supports both standard (100 kbps) and fast (400 kbps) twi modes. address arbitration is not implemented, so multiple master applications are not support ed. the twi m aster controller?s serial c lock (scl) is produced by a programmable clock g enerator. scl is produced by dividing down 12 m hz according to this equation : exp lin mhz rate 2 * ) 1 ( 12 + = 8 -18 120 - 035x - 000 rev. 1.2 final
EM351 / em357 exp is the value written to the scx _rateexp register and lin is the value written to the scx _ratelin regist er. table 8 - 8 shows the rate settings for standard - mode twi (100 kbps) and fast - mode twi (400 kbps) operation. table 8 - 8 . twi clock rate programming clock rat e scx _ratelin scx _rateexp 100 kbps 14 3 375 kbps 15 1 400 kbps 14 1 note: at 400 kbps, the philips i 2 c bus specification requires the minimum low period of scl to be 1.3 s , but on the em35x it is 1.25 s . if a slave device requires strict compliance with scl timing, the clock rate must be lowered to 375 kbps. the em35x supports clock stretching. the slave device can hold scl low on any received or transmitted data bit. this inhibit s further data transfers until scl is allowed to go high again. 8.5.3 constructing frames the twi master c ontroller supports generating various frame segments by means of the sc_twistart , sc_twistop , sc_twisend , and sc_twirecv bits in the scx _twictrl1 registers. table 8 - 9 summarizes these frames. 8 -19 120 - 035x - 000 rev. 1.2 final
EM351 / em357 table 8 - 9 . twi master frame segments scx _twictrl1 frame segments sc_twixxxx 1 start send recv stop 1 0 0 0 twi re-start segment - after transmit or frame with nack sda out sda outslave scl outslave scl out twi start segment sda out sda outslave scl outslave scl out 0 1 0 0 scl out tx[7] tx[6] tx[5] tx[4] tx[3] tx[2] tx[1] tx[0] sda out sda outslave scl outslave (n)ack twi transmit segment - after (re-)start frame scl out tx[7] tx[6] tx[5] tx[4] tx[3] tx[2] tx[1] tx[0] sda out sda outslave scl outslave (n)ack twi transmit segment ? after transmit with ack 0 0 1 0 scl out rx[7] rx[6] rx[5] rx[4] rx[3] rx[2] rx[1] rx[0] sda out sda outslave scl outslave (n)ack twi receive segment ? transmit with ack scl out rx[7] rx[6] rx[5] rx[4] rx[3] rx[2] rx[1] rx[0] sda out sda outslave scl outslave (n)ack twi receive segment - after receive with ack 0 0 0 1 twi stop segment - after frame with nack or stop sda out sda outslave scl outslave scl out 0 0 0 0 no pending frame segment 1 - - 1 1 1 - - - 1 1 - - - 1 1 illegal 1 the notation xxx means that the corresponding column header below is inserted to form the field name. 8 -20 120 - 035x - 000 rev. 1.2 final
EM351 / em357 full twi frames have to be constr ucted by software from individual twi segments. all necessary segment transitions are shown in figure 8 - 2 . ack or nack generation of a twi receive frame segment is determined with the sc_twiack bit in the scx _twictrl2 register. figure 8 - 2 . twi segment transitions generation of a 7 - bit address is accomplished with one transmit segment. the upper 7 bits of the transmitted character contain the 7 - bit address. the remaining lower bit contains the command type (?read? or ?write?). generati on of a 10 - bit address is accomplished with two transmit segments. the upper 5 bits of the first transmit character must be set to 0x1e . the next 2 bits are for the 2 most significant bits of the 10 - bit address. the remaining lower bit contains the command type (?read? or ?write?). the second transmit segment is for the remaining 8 bits of the 10 - bit address. transmitted and received characters are accessed through the scx _data register. to initiate ( r e )start and stop segments , set the sc_twistart or sc_twistop bit in the scx _twictrl1 register, then wait until the bit is clear . alternatively, the sc_twicmdfin bit in the scx _twistat can be used for waiting. to initiate a transmit segment, write the data to the scx _data data register, then set the sc_twi send bit in the scx _twictrl1 register, and finally wait until the bit is clear . alternatively the sc_twitxfin bit in the scx _twistat register can be used for waiting. to initiate a receive segment , set the sc_twirecv bit in the scx _twictrl1 register, wait until it is clear , and then read from the scx _data register. alternatively, the sc_twirxfin bit in the scx _twistat register can be used for waiting. now the sc_twirxnak bit in the scx _twistat register indicates if a nack or ack was received from a twi slave device. 8.5.4 interrupts twi master controller interrupts are generated on the following events: ? bus command ( sc_twistart/sc_twistop ) completed (0 to 1 transition of sc_twicmdfin ) ? character transmitted and slave device responded with nack receive segment with nack receive segment with ack idle start segment stop segment transmit segment received ack ? no yes 8 -21 120 - 035x - 000 rev. 1.2 final
EM351 / em357 ? character trans mitted (0 to 1 transition of sc_twitxfin ) ? character received (0 to 1 transition of sc_twirxfin ) ? received and lost character while r eceive fifo was full (r eceive overrun error) ? transmitted character while t ransmit fif o was empty (t ransmit underrun error) t o enable cpu interrupts, set the desired interrupt bits in the second - level int_ scx cfg register, and enable the top - level scx interrupt in the nvic by writing the int_ scx bit in the int_cfgset register. 8.5.5 registers refer to registers (in the spi master mode section) for a description of the scx _ data , scx_ratelin, and scx_rateexp register s . scx_twistat sc1_twistat twi status register address: 0x4000c844 reset: 0x0 sc2_twistat twi status register address: 0x4000c044 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 sc_twicmdfin sc_twirxfin sc_twitxfin sc_twirxnak bitname bitfield access description sc_twicmdfin [3] r this bit is set when a start or stop command completes. it clears on the next twi bus activity. sc_twirxfin [2] r this bit is set when a byte is received. it clears on the next twi bus activity. sc_twitxfin [1] r this bit is set when a byte is transmitted. it clears on the next twi bus activity. sc_twirxnak [0] r this bit is set when a nack is received from the slave. it clears on the next twi bus activity. 8 -22 120 - 035x - 000 rev. 1.2 final
EM351 / em357 scx_twictrl1 sc1_twictrl1 twi control register 1 address: 0x4000c84c reset: 0x0 sc2_twictrl1 twi control register 1 address: 0x4 000c04c reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 sc_twistop sc_twistart sc_twisend sc_twirecv bitname bitfield access description sc_twistop [3] rw setting this bit sends the stop command. it clears when the command completes. sc_twistart [2] rw setting this bit sends the start or repeated start command. it clears when the command completes. sc_twisend [1] rw setting this bit transmits a byte. it clears when the command completes. sc_twirecv [0] rw setting this bit receives a byte. it clears when the command completes. 8 -23 120 - 035x - 000 rev. 1.2 final
EM351 / em357 scx_twictrl2 sc1_twictrl2 twi control register 2 address: 0x4000c850 reset: 0x0 sc2_twictrl2 twi control r egister 2 address: 0x4000c050 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 sc_twiack bitname bitfield access description sc_twiack [0] rw setting this bit signal s ack after a received byte. clearing this bit signal s nack after a received byte. 8.6 uart - universal asynchronous receiver / transmitter the sc1 uart is enabled by writing 1 to sc1_mode . the sc2 serial controller does not include uart functions. the uart supports the following features: ? flexible b aud rate clock ( 300 b ps to 921 .6 k bps) ? data b its (7 or 8) ? parity bits (none, odd, or even) ? stop bits (1 or 2) ? false start bit and noise filtering ? r eceive and transmit fifos ? optional rts/cts flow control ? r eceive and transmit dma channels 8.6.1 gpio usage the uart uses two sign als to transmit and receive serial data: ? txd (transmitted data) ? serial data sent by the em35x ? rxd (received data) ? serial data received by the em35x if rts/cts flow control is enabled , these two signals are also used: ? nrts (request to send) ? indicates the em35x is able to receive data ? ncts (clear to send) ? inhibits sending data from the em35x if not asserted 8 -24 120 - 035x - 000 rev. 1.2 final
EM351 / em357 the gpio pins assigned to these signal s are shown in table 8 - 10. table 8 - 10 . uart gpio usage txd rxd ncts 1 nrts 1 direction output input input output gpio configuration a lternate o utput (push - pull) input input alternate output (push - pull) sc1 pin pb 1 pb 2 pb 3 pb 4 1 only used if rts/cts hardware flow control is enabled. 8.6.2 set up and configuration the uart baud rate clock is produced by a progr ammable baud generator starting from the 24 hz clock: f n mhz baud + = 2 24 the integer portion of the divisor , n , is written to the sc1_uartper register and the fractional part , f, to the sc1_uartfrac register. table 8 - 11 shows the values used to generate some common baud rates and their associated clock frequency error. the uart requires an i nternal clock that is at least eight times the baud rate clock, so the minimum allowable setting for sc1_uartper is 8. table 8 - 11 . uart baud rate divisors for common baud rates baud rate (bits/ s ec ) sc1_uartper sc1_uartfrac baud rate error (%) 300 40000 0 0 2400 5000 0 0 4800 2500 0 0 9600 1250 0 0 19200 625 0 0 38400 312 1 0 57600 208 1 - 0.08 115200 104 0 + 0.16 230400 52 0 + 0.16 460800 26 0 + 0.16 921600 13 0 + 0.16 the uart can miss bytes when the inter - byte gap is long or there is a baud rate mismatch between receiver and transmitter. the uart may detect a parity and/or framing error on the corrupted byte, but there will not nece ssarily be any error detected. 8 -25 120 - 035x - 000 rev. 1.2 final
EM351 / em357 the uart is best operated in systems where the other side of the communication link also uses a crystal as its timing reference, and baud rates should be selected to minimize the baud rate mismatch to the c rystal tolerance. additionally, uart protocols should contain some form of error checking ( for example crc) at the packet level to detect, and retry in the event of errors. since the probability of corruption is low, there would only be a small effect on uart throughput due to retries. errors may occur when: ( ) ferror baud tgap ? 106 where tgap = inter - byte gap in seconds b aud = baud rate in bps ferror = relative frequency error in ppm for example, if the baud rate tolerance between receive and transmit is 20 0 ppm (reasonable if both sides are derived from a crystal), and the baud rate is 115200 bps, then errors will not occur until the inter - byte gap exceeds 43 ms. if the gap is exceeded then the chance of an error is essentially random, with a probability of approximately p = baud / 24e6. at 115200 bps, the probability of corruption is 0.5%. the uart character frame format is determined by four bits in the sc1_uartcfg register: ? sc_uart8bit specifies the number of data bits in received and transmitted characters. if this bit is clear, characters have 7 data bits; if set, characters have 8 data bits. ? sc_uart2stp selects the number of stop bi ts in transmitted characters. ( only one stop bit is required in received characters .) if this bit is clear, charact ers ar e transmitted with one stop bit ; if set, characters are transmitted with two stop bits. ? sc_uartpar controls whether or not received and transmitted characters include a parity bit . if sc_uartpar is clear, characters do not contain a parity bit, otherwise , characters do contain a parity bit. ? sc_uartodd specifies whether transmitted and received parity bits contain odd or even parity. if this bit is clear, the parity bit is even, and if set , the parity bit is odd. even parity is the exclusive - or of all of the data bits, and odd parity is the inverse of the even parity value. sc_uartodd has no effect if sc_uartpar is clear. a uart character frame contains, in sequence: ? t he start bit ? t he least signi ficant data bit ? t he remain ing data bits ? i f parity is enabled, the parity bit ? t he stop bit, or bits, if 2 stop bits are selected . figure 8 - 3 shows the uart character frame format , with optional bits indicated . dependin g on the options chosen for the character frame, the length of a character frame ranges from 9 to 12 bit times. note that a synchronous serial data may have arbitrarily long idle periods between characters. when idle, serial data (txd or rxd) is held in the high state . s erial data transitions to the low state in the start bit at the beginning of a character frame. 8 -26 120 - 035x - 000 rev. 1.2 final
EM351 / em357 figure 8 - 3 . uart character frame format idle time start bit data bit 0 data bit 1 data bit 2 data bit 3 data bit 4 data bit 5 data bit 6 data bit 7 parity bit stop bit stop bit next start bit or idletime uart character frame format ( optional sections are in italics ) txd or rxd 8.6.3 fifos c haracters trans mitted and received by the uart are buffered in the transmit and receive fifos that are both 4 entries deep (see figure 8 - 4 ) . when software writes a character to the sc 1 _data register, it is pushed onto the transmit fifo. similarly, when software reads from the sc 1 _data register, the character returned is pull ed f rom the receive fifo. if the transmit and receive dma channels are used, the dma channels also write to and read from the transmit and receive fifos. figure 8 - 4 . uart fifos receive shift register sc 1 _ data ( read ) transmit shift register sc 1 _ data ( write ) rxd txd parity / frame errors sc 1 _ uartstat receive fifo transmit fifo cpu and dma channel access 8.6.4 rts/ct s flow control rts/cts flow control, also called hardware flow control, uses two signals (nrts and ncts) in addition to received and transmitted data (see figure 8 - 5 ). flow control is used by a data receiver to prevent buffer over flow , by signal ing an external device when it is and is not allowed to transmit. figure 8 - 5 . rts/cts flow control connections other device uart receiver uart transmitter em350 uart transmitter uart receiver rxd txd nrts ncts txd rxd ncts nrts t he uart rts/cts flow control options are selected by the sc_uartflow and sc_uartauto bits in the sc1_uartcfg register (see table 8 - 12 ) . whenever the sc_uartflow bit is set, the uart will not start transmitting a character unless ncts is low (asserted). if ncts transitions to the high state (deasserts) while a character is b eing transmitted, transmission of that character continue s until it is complete. 8 -27 120 - 035x - 000 rev. 1.2 final
EM351 / em357 if the sc_uartauto bit is set, nrts is controlled automatically by hardware: nrts is put in to the low state (asserted) when the receive fifo has room for at least two characte rs, otherwise is it in the high state (unasserted). if sc_uartauto is clear, software controls the nrts output by setting or clearing the sc_uartrts bit in the sc1_uartcfg register . software control of nrts is useful if the external serial device cannot st op transmitting characters promptly when nrts is set to the high state (deasserted). table 8 - 12 . uart rts/cts flow control configurations sc1_uartcfg pins used operating mode sc_uartxxx 1 flow auto rts 0 - - txd, rxd n o rts/cts flow control 1 0 0/1 txd, rxd, ncts, nrts flow control using rts/cts with software control of nrts: nrts controlled by sc_uartrts bit in sc1_uartcfg register 1 1 - txd, rxd, ncts, nrts flow control using rts/cts with hardware control of nrts: nrts is asserted if room for at least 2 characters in receive fifo 1 the notation xxx means that the corresponding column header below is inserted to form the field name. 8.6.5 dma the dma channels section describes how to configure and use the serial receive and transmit dma channels. t he receive dma channel has special provision s to record uart receive er rors. when the dma channel tra nsfers a character from the receive fifo to a buffer in memory , it checks the stored parity and frame error status flags. when an error is flagged, the sc1_rxerra/b register is updated, marking the offset to the first received character with a parity or fr ame error. similarly if a receive overrun error occur s , the sc1_rxerra/b registe rs mark the error offset. the receive fifo hardware gener ate s the int_scrxovf inter rupt and dma status register indicate s the error immediately , but in this case the error offs et is 4 characters ahead of the actual overflow at the input to the receive fifo. t wo conditions will clear the error indication: setting the appropriate sc_ rxdmarst bit in the sc1_dmactrl register, or loading the appropriate dma buffer after it has unloaded. 8.6.6 interrupts uart interrup ts are generated on the following events: ? transmit fifo empty and last character shifted out ( depending on scx _intmode , either the 0 to 1 transi tion or the high level of sc_uarttxidle ) ? transmit fifo changed from full to not full ( depending on scx _intmode , either the 0 to 1 transi tion or the high level of sc_uarttxfree ) ? receive fifo changed from empty to not empty ( depending on scx _intmode , either the 0 to 1 trans i tion or the high level of sc_uartrxval ) ? transmit dma buffer a/b complete (1 to 0 transition of sc_txacta/b ) ? receive dma buffer a/b complete (1 to 0 transition of sc_rxacta/b ) ? character received with p arity error ? character rece ived with f rame error ? charact er received and lost when r eceive fifo was full (receive o verrun error) to enable cpu interrupts, set the desired interrupt bits in the second - level int_ scx cfg register, and enable the top - level scx interrupt in the nvic by writing the int_ scx bit in the int_cfgset register. 8 -28 120 - 035x - 000 rev. 1.2 final
EM351 / em357 8.6.7 registers refer to registers (in the spi master mode section) for a description of the scx _ data register. sc1_uartstat uart status register address: 0x4000c848 reset: 0x40 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 sc_uarttxidle sc_uartparerr sc_uartfrmerr sc_uartrxovf sc_uarttxfree sc_uartrxval sc_uartcts bitname bitfield access description sc_uarttxidle [6] r this bit is set when both the transmit fifo and the transmit serializer are empty. sc_uartparerr [5] r this bit is set when the byte in the data register was received with a parity error. this bit is updated when the data register is read, and is cleared if the receive fifo is empty. sc_uartfrmerr [4] r this bit is set when the byte in the data register was received with a frame error. this bit is updated when the data register is read, and is cleared if the receive fifo is empty. sc_uartrxovf [3] r this bit is set when the receive fifo has been overrun. this occurs if a byte is received when the receive fifo is full. this bit is cleared by reading the data register. sc_uarttxfree [2] r this bit is set when the transmit fifo has space for at least one by te. sc_uartrxval [1] r this bit is set when the receive fifo contains at least one byte. sc_uartcts [0] r this bit shows the logical state (not voltage level) of the ncts input: 0: ncts is deasserted (pin is high, 'xoff', rs232 negative voltage); the uart is inhibited from starting to transmit a byte. 1: ncts is asserted (pin is low, 'xon', rs232 positive voltage); the uart may transmit. 8 -29 120 - 035x - 000 rev. 1.2 final
EM351 / em357 sc1_uartcfg uart configuration register address: 0x4000c85c r eset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 sc_uartauto sc_uartflow sc_uartodd sc_uartpar sc_uart2stp sc_uart8bit sc_uartrts bitname bitfield access description sc_uartauto [6] rw set this bit to enable automatic nrts control by hardware (sc_uartflow must also be set). when automatic control is enabled, nrts will be deasserted when the receive fifo has space for only one more byte (inhibits transmission from the other device) and will be asserted if it has space for more than one byte (enables transmission from the other device). the sc_uartrts bit in this register has no effec t if this bit is set. sc_uartflow [5] rw set this bit to enable using nrts/ncts flow control signals. clear this bit to disable the signals. when this bit is clear, the uart transmitter will not be inhibited by ncts. sc_uartodd [4] rw if parity is enabled, specifies the kind of parity. 0: even parity. 1: odd parity. sc_uartpar [3] rw specifies whether to use parity bits. 0: don't use parity. 1: use parity. sc_uart2stp [2] rw number of stop bits transmitted. 0: 1 stop bit. 1: 2 stop bits. sc_uart8bit [1] rw number of data bits. 0: 7 data bits. 1: 8 data bits. sc_uartrts [0] rw nrts is an output to control the flow of serial data sent to the em35x from another device. this bit directly controls the output at the nrts pin (sc_uartflow must b e set and sc_uartauto must be cleared). when this bit is set, nrts is asserted (pin is low, 'xon', rs232 positive voltage); the other device's transmission is enabled. when this bit is cleared, nrts is deasserted (pin is high, 'xoff', rs232 negative voltag e), the other device's transmission is inhibited. 8 -30 120 - 035x - 000 rev. 1.2 final
EM351 / em357 sc1_uartper uart baud rate period register address: 0x4000c868 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 sc_uartper 7 6 5 4 3 2 1 0 sc_uartper bitname bitfield access description sc_uartper [15:0] rw the integer part of baud rate period (n) in the equation: rate = 24mhz / ( (2 * n) + f ) 8 -31 120 - 035x - 000 rev. 1.2 final
EM351 / em357 sc1_uartfrac uart baud rate fractional period register address: 0x4000c86c reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 sc_uartfrac bitname bitfield access description sc_uartfrac [0] rw the fractional part of the baud rate period (f) in the equation: rate = 24mhz / ( (2 * n) + f ) 8.7 dma channels the em35x serial dma channels enable efficient, high - speed operation of the spi and uart controllers by reducing the load on the cpu as well as decreasing the frequency of interrupts that it must service. the transmit and receive dma channels can transfer data betw een the transmit and receive fifos and the dma buffers in main memory as quickly as it can be transmitted or received. once software defines , configures , and activates the dma, it only needs to handle an interrupt when a transmit buffer has been emptied or a receive buffer has been filled. the dma channels each support two memory buffers, labeled a and b, and can alternate (?ping - pong?) between them automatically to allow continuous communication without critical interrupt timing. note: dma memory buffer terminol ogy ? load - make a buffer available for the dma channel to use ? pending ? a buffer loaded but not yet active ? active - the buffer that will be used for the next dma transfer ? unload ? dma channel action when it has finished with a buffer ? idle ? a buffer that h as not been loaded, or has been unloaded to use a dma channel, software should follow these steps: ? reset the dma channel by setting the sc_txdmarst (or sc_rxdmarst ) bit in the scx _dmactrl register. ? set up the dma buffers. the two dma buffers, a and b, are defined by writing the start address to scx _txbega/b (or scx _rxbega/b ) and the (inclusive) end address to scx _txenda/b (or scx _rxenda/b ). note that dma buffers must be in ram. ? configure and initiali ze scx for the desired operating mode. ? enable second - level interrupts triggered when dma buffers unload by setting the int_sctxulda/b (or int_scrxulda/b ) bits in the int_ scx flag register. ? enable top - level nvic interrupts by setting the int_scx bit in the i nt_cfgset register . ? start the dma by loading the dma buffers by setting the sc_txloda/b (or sc_rxloda/b ) bits in the scx _dmactrl register. 8 -32 120 - 035x - 000 rev. 1.2 final
EM351 / em357 a dma buffer?s end address, scx _txenda/b (or scx _rxenda/b ), can be written while the buffer is loaded or active. thi s is useful for receiving messages that contain a n initial byte count, since it allows software to set the buffer end address at the last byte of the message. as the dma channel transfers data between the transmit or receive fifo and a memory buffer, the d ma count register contains the byte offset from the start of the buffer to the address of the next byte that will be written or read. a transmit dma channel has a single dma count register ( scx _txcnt ) that applies to whichever transmit buffer is active, bu t a receive dma channel has two dma count registers ( scx _rxcnta/b ) , one for each receive buffer. the dma count register contents are preserved until the corresponding buffer, or either buffer in the case of the transmit dma count, is loaded , or until the d ma is reset. the receive dma count register may be written while the corresponding buffer is loaded. if the buffer is not loaded, writing the dma count register also loads the buffer while preserving the count value written. this feature can simplify handl ing uart receive errors. the dma channel stops using a buffer and unloads it when the following is true: (dma buffer start address + dma buffer count) > dma buffer end address typically a transmit buffer is unloaded after all its data has been sent, and a receive buffer is unloaded after it is filled with data, but writing to the buffer end address or buffer count registers can also cause a buffer to unload early. serial controller dma channels include additional features specific to the spi and uart operation and are described in those sections. 8 -33 120 - 035x - 000 rev. 1.2 final
EM351 / em357 8.7.1 registers scx_dmactrl sc1_dmactrl serial dma control register address: 0x4000c830 reset: 0x0 sc2_dmactrl serial dma control register address: 0x4000c030 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 sc_txdmarst sc_rxdmarst sc_txlodb sc_txloda sc_rxlodb sc_rxloda bitname bitfield access description sc_txdmarst [5] w setting this bit resets the transmit dma. the bit clears automatically. sc_rxdmarst [4] w setting this bit resets the receive dma. the bit clears automatically. sc_txlodb [3] rw setting this bit loads dma transmit buffer b addresses and allows the dma controller to start processing transmit buffer b. if both buffer a and b are loaded simultaneously, buffer a will be used first. this bit is cleared when dma completes. writing a zero to this bit has no effect. reading this bit returns dma buffer status: 0: dma processing is complete or idle. 1: dma processing is active or pending. sc_txloda [2] rw setting this bit loads dm a transmit buffer a addresses and allows the dma controller to start processing transmit buffer a. if both buffer a and b are loaded simultaneously, buffer a will be used first. this bit is cleared when dma completes. writing a zero to this bit has no effe ct. reading this bit returns dma buffer status: 0: dma processing is complete or idle. 1: dma processing is active or pending. sc_rxlodb [1] rw setting this bit loads dma receive buffer b addresses and allows the dma controller to start processing receive buffer b. if both buffer a and b are loaded simultaneously, buffer a will be used first. this bit is cleared when dma completes. writing a zero to this bit has no effect. reading this bit returns dma buffer status: 0: dma processing is complete or idle. 1 : dma processing is active or pending. sc_rxloda [0] rw setting this bit loads dma receive buffer a addresses and allows the dma controller to start processing receive buffer a. if both buffer a and b are loaded simultaneously, buffer a will be used first . this bit is cleared when dma completes. writing a zero to this bit has no effect. reading this bit returns dma buffer status: 0: dma processing is complete or idle. 1: dma processing is active or pending. 8 -34 120 - 035x - 000 rev. 1.2 final
EM351 / em357 scx_dmastat sc1_dmastat serial dma status regist er address: 0x4000c82c reset: 0x0 sc2_dmastat serial dma status register address: 0x4000c02c reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 sc_rxssel sc_rxfrmb sc_rxfrma 7 6 5 4 3 2 1 0 s c_ r x pa r b sc_rxpara sc_rxovfb s c_ r x o v fa sc_txactb sc_txacta sc_rxactb sc_rxacta bitname bitfield access description sc_rxssel [12:10] r status of the receive count saved in scx_rxcntsaved (spi slave mode) when nssel deasserts. cleared when a receive buffer is loaded and when the receive dma is reset. 0: no count was saved because nssel did not deassert. 2: buffer a's count was saved, nssel deasserted once. 3: buffer b's count was saved, nssel deasserted once. 6: buffer a's count was saved, nssel deasserted more than once. 7: buffer b's count was saved, nssel deasserted more than once. 1, 4, 5: reserved. sc_rxfrmb [9] r this bit is set when dma receive buffer b reads a byte with a frame error from the receive fifo. it is cleared the next time buffer b is loaded or when the receive dma is reset. (sc1 in uart mode only) sc_rxfrma [8] r this bit is set when dma receive buffer a reads a byte with a frame error from the receive fifo. it is cleared the next time buffer a is loaded or when the r eceive dma is reset. (sc1 in uart mode only) sc_rxparb [7] r this bit is set when dma receive buffer b reads a byte with a parity error from the receive fifo. it is cleared the next time buffer b is loaded or when the receive dma is reset. (sc1 in uart mo de only) s c _rx par a [6] r this bit is set when dma receive buffer a reads a byte with a parity error from the receive fifo. it is cleared the next time buffer a is loaded or when the receive dma is reset. (sc1 in uart mode only) sc_rxovfb [5] r this bit is set when dma receive buffer b was passed an overrun error from the receive fifo. neither receive buffer was capable of accepting any more bytes (unloaded), and the fifo filled up. buffer b was the next buffer to load, and when it drained the fifo the ov errun error was passed up to the dma and flagged with this bit. cleared the next time buffer b is loaded and when the receive dma is reset. sc_rxovfa [4] r this bit is set when dma receive buffer a was passed an overrun error from the receive fifo. neither receive buffer was capable of accepting any more bytes (unloaded), and the fifo filled up. buffer a was the next buffer to load, and when it drained the fifo the overrun error was passed up to the dma and flagged with this bit. cleared the next tim e buffer a is loaded and when the receive dma is reset. sc_txactb [3] r this bit is set when dma transmit buffer b is active. sc_txacta [2] r this bit is set when dma transmit buffer a is active. sc_rxactb [1] r this bit is set when dma receive buffer b is active. sc_rxacta [0] r this bit is set when dma receive buffer a is active. 8 -35 120 - 035x - 000 rev. 1.2 final
EM351 / em357 scx_txbega sc1_txbega transmit dma begin address register a address: 0x4000c810 reset: 0x20000000 sc2_txbega transmit dma begin address register a address: 0x4000c010 re set: 0x20000000 31 30 29 28 27 26 25 24 0 0 1 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 sc_txbega 7 6 5 4 3 2 1 0 sc_txbega bitname bitfield access description sc_txbega [1 3 :0] rw dma transmit buffer a start address. 8 -36 120 - 035x - 000 rev. 1.2 final
EM351 / em357 scx_txbegb sc1_txbegb transmit dma begin address register b address: 0x4000c818 reset: 0x20000000 sc2_txbegb transmit dma begin address register b address: 0x4000c018 reset: 0x20000000 31 30 29 28 27 26 25 24 0 0 1 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 sc_txbegb 7 6 5 4 3 2 1 0 sc_txbegb bitname bitfield access description sc_txbegb [ 13 :0] rw dma transmit buffer b start address. 8 -37 120 - 035x - 000 rev. 1.2 final
EM351 / em357 scx_txenda sc1_txenda transmit dma end address register a address: 0x4000c814 reset: 0x20000000 sc2_txenda transmit dma end address register a address: 0x4000c014 reset: 0x20000000 31 30 29 28 27 26 25 24 0 0 1 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 sc_txenda 7 6 5 4 3 2 1 0 sc_txenda bitname bitfield access description sc_txenda [1 3 :0] rw address of the last byte that will be read from the dma transmit buffer a. 8 -38 120 - 035x - 000 rev. 1.2 final
EM351 / em357 scx_txendb sc1_txendb transmit dma end address register b address: 0x4000c81c reset: 0x20000000 sc2_txendb transmit dma end address register b address: 0x4000c01c reset: 0x20000000 31 30 29 28 27 26 25 24 0 0 1 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 sc_txendb 7 6 5 4 3 2 1 0 sc_txendb bitname bitfield access description sc_txendb [1 3 :0] rw address of the last byte that will be read from the dma transmit buffer b. 8 -39 120 - 035x - 000 rev. 1.2 final
EM351 / em357 scx_txcnt sc1_txcnt transmit dma count register address: 0x4000c828 reset: 0x0 sc2_txcnt transmit dma count register address: 0x4000c028 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 sc_txcnt 7 6 5 4 3 2 1 0 sc_txcnt bitname bitfield access description sc_txcnt [1 3 :0] r the offset from the start of the active dma transmit buffer from which the next byte will be read. this register is set to zero when the buffer is loaded and when the dma is reset. 8 -40 120 - 035x - 000 rev. 1.2 final
EM351 / em357 scx_rxbega sc1_rxbega receive dma begin address register a address: 0x4000c800 reset: 0x20000000 sc2_rxbega receive dma begin address register a address: 0x4000c000 reset: 0x20000000 31 30 29 28 27 26 25 24 0 0 1 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 sc_rxbega 7 6 5 4 3 2 1 0 sc_rxbega bitname bitfield access description sc_rxbega [1 3 :0] rw dma receive buffer a start address. 8 -41 120 - 035x - 000 rev. 1.2 final
EM351 / em357 scx_rxbegb sc1_rxbegb receive dma begin address register b address: 0x4000c808 reset: 0x20000000 sc2_rxbegb receive dma begin address register b address: 0x4000c008 reset: 0x20000000 31 30 29 28 27 26 25 24 0 0 1 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 sc_rxbegb 7 6 5 4 3 2 1 0 sc_rxbegb bitname bitfield access description sc_rxbegb [1 3 :0] rw dma receive buffer b start address. 8 -42 120 - 035x - 000 rev. 1.2 final
EM351 / em357 scx_rxenda sc1_rxenda receive dma end address register a address: 0x4000c804 reset: 0x20000000 sc2_rxenda receive dma end address register a ddress: 0x4000c004 reset: 0x20000000 31 30 29 28 27 26 25 24 0 0 1 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 sc_rxenda 7 6 5 4 3 2 1 0 sc_rxenda bitname bitfield access description sc_rxenda [1 3 :0] rw address of the last byte that will be written in the dma receive buffer a. 8 -43 120 - 035x - 000 rev. 1.2 final
EM351 / em357 scx_rxendb sc1_rxendb receive dma end address register b address: 0x4000c80c reset: 0x20000000 sc2_rxendb receive dma end address register b address: 0x4000c00c reset: 0x20000000 31 30 29 28 27 26 25 24 0 0 1 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 sc_rxendb 7 6 5 4 3 2 1 0 sc_rxendb bitname bitfield access description sc_rxendb [1 3 :0] rw address of the last byte that will be written in the dma receive buffer b. 8 -44 120 - 035x - 000 rev. 1.2 final
EM351 / em357 scx_rxcnta s c 1 _r x cn ta receive dma count register a address: 0x4000c820 reset: 0x0 s c 2 _r x cn ta receive dma count register a address: 0x4000c020 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 sc_rxcnta 7 6 5 4 3 2 1 0 sc_rxcnta bitname bitfield access description sc _rxc nta [1 3 :0] rw the offset from the start of dma receive buffer a at which the next byte will be written. this register is set to zero when the buffer is loaded and when the dma is reset. if this register is written when the buffer is not loaded, the buffer is loaded. 8 -45 120 - 035x - 000 rev. 1.2 final
EM351 / em357 scx_rxcntb sc1_rxcntb receive dma count register b address: 0x4000c824 reset: 0x0 sc2_rxcntb receive dma count register b address: 0x4000c024 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 sc_rxcntb 7 6 5 4 3 2 1 0 sc_rxcntb bitname bitfield access description sc_rxcntb [1 3 :0] rw the offset from the start of dma receive buffer b at which the next byte will be written. this register is set to zero when the buffer is loaded and when the dma is reset. if this register is written when the buffer is not loaded, the buffer is loaded. 8 -46 120 - 035x - 000 rev. 1.2 final
EM351 / em357 scx_rxcntsaved sc1_rxcntsaved saved receive dma count register address: 0x4000c870 reset: 0x0 sc2_rxcntsaved saved receive dma count register address: 0x4000c070 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 sc_rxcntsaved 7 6 5 4 3 2 1 0 sc_rxcntsaved bitname bitfield access description s c _rxc n ts ave d [1 3 :0] r receive dma count saved in spi slave mode when nssel deasserts. the count is only saved the first time nssel deasserts. 8 -47 120 - 035x - 000 rev. 1.2 final
EM351 / em357 scx_rxerra sc1_rxerra dma first receive error register a address: 0x4000c834 reset: 0x0 sc2_rxerra dma first receive error register a address: 0x4000c034 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 sc_rxerra 7 6 5 4 3 2 1 0 sc_rxerra bitname bitfield access description sc_rxerra [1 3 :0] r the offset from the start of dma receive buffer a of the first byte received with a parity, frame, or overflow error. note that an overflow error occurs at the input to the receive fifo, so this offset is 4 bytes before the overflow position. if there is no error, it reads zero. this register will not be updated by subsequent errors until the buffer unloads and is reloaded, or the receive dma is reset. 8 -48 120 - 035x - 000 rev. 1.2 final
EM351 / em357 scx_rxerrb sc1_rxerrb dma first receive error register b address: 0x4000c838 reset: 0x0 sc2_rxerrb dma first receive error register b address: 0x4000c038 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 sc_rxerrb 7 6 5 4 3 2 1 0 sc_rxerrb bitname bitfield access description sc_rxerrb [1 3 :0] r the offset from the start of dma receive buffer b of the first byte received with a parity, frame, or overflow error. note that an overflow error occurs at the input to the receive fifo, so this offset is 4 bytes before the overflow position. if t here is no error, it reads zero. this register will not be updated by subsequent errors until the buffer unloads and is reloaded, or the receive dma is reset. 8 -49 120 - 035x - 000 rev. 1.2 final
EM351 / em357 9 general purpose timers (tim1 and tim2) 9.1 introduction each of the em35x ?s two general - purpose timers consists of a 16 - bit auto - reload counter driven by a programmable prescaler . they may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms ( output compare and pwm). pulse lengths and waveform periods can be modulated from a few microseconds to sev eral milliseconds using the timer prescaler. the timers are completely independent, and do not share any resources. they can be synchronized together as described in the timer synchronization section. the two general - purpose timers, tim1 and tim2, have the following features: ? 16- bit up, down, or up/down auto - reload counter. ? programmable prescaler to divide the counter clock by any power of two from 1 through 32768. ? 4 i ndependent channels for: ? input capture ? output compare ? pwm generation (edge - and center - aligned mode) ? one - pulse mode output ? synchronization circuit to control the timer with external signals and to interconnect the timers. ? flexible clock source selection: ? p eripheral clock (pclk at 6 or 12 mhz) ? 32 .768 khz external clock (if available) ? 1 khz clock ? gpio input ? interrupt generation on the following events: ? update: counter overflow/underflow, counter initialization (software or internal/external trigger) ? trigger event (counter start, stop, initialization or count by internal/external trigger) ? input capture ? output compare ? supports incremental (quadrature) encoders and hall sensors for positioning applications. ? trigger input for external clock or cycle - by - cycle curr ent management. figure 9 - 1 shows an over view of a timer?s internal structure. note: because the two timers are identical, the notation timx refers to either tim1 or tim2. for example, timx_psc refers to both tim1_psc and tim2_psc. similarly, ?y? refers to any of the four channels of a given timer, so for example, ocy refers to oc1, oc2, oc3, and oc4. 9 -1 120 - 035x - 000 rev. 1.2 final
EM351 / em357 figure 9 - 1 . general - purpos e timer block diagra m note: the internal signals shown in figure 9 - 1 are described in the timer signal descriptions section , and are used throughout the te xt to describe how the timer components are interconnected. 9 -2 120 - 035x - 000 rev. 1.2 final
EM351 / em357 9.2 gpio usage the timers can optionally use gpios in the pa and pb ports for external inputs or outputs. as with all em35x digital inputs, a gpio used as a timer input can be shared with other uses of the same pin. available timer inputs include an external timer clock, a clock mask, and four input channels. any gpio used as a timer output must be configured as an alternate output and is controlled only by the timer. many of the gpios that can be ass igned as timer outputs can also be used by another on - chip peripheral such as a serial controller. us ing a gpio as a timer output takes precedence over another peripheral function, as long as the channel is configured as an output in the timx_ccmr1 registe r and is enabled in the timx_ccer register. the gpios that can be used by timer 1 are fixed, but the gpios that can be used as timer 2 channels can be mapped to either of two pins, as shown in table 9 - 1 . the timer 2 option register (tim2_or) has four single bit fields (tim_remapcy) that control whether a timer 2 channel is mapped to its default gpio in port pa, or remapped to a gpio in pb. table 9 - 1 specifies the pins that may be assigned to timer 1 and timer 2 functions. table 9 - 1 . timer gpio usage signal (direction) timxc1 (in or out) timxc2 (in or out) timxc3 (in or out) timxc4 (in or out) timxclk (in) timxmsk (in) timer 1 pb6 pb7 pa6 pa7 pb0 pb5 timer 2 (tim_remapcy = 0) pa0 pa3 pa1 pa2 pb5 pb0 timer 2 (tim_remapcy = 1) pb1 pb2 pb3 pb4 pb5 pb0 the timxclk and timxmsk inputs can be used o nly in the external clock modes; refer to the external clock source mode 1 and external clock source mode 2 sections for details concerning their use. 9.3 timer functional description 9.3.1 time - base unit the main block of the general purpose timer is a 16 - bit counter with its related auto - reload register. the counter can count up, down, or alternate up and down. the counter clock can be divided by a prescaler. the counter, the auto - reload register, and the prescaler register can be written to or read by software. this is true even when the counter is running. the time - bas e unit includes: ? counter register (timx_cnt) ? prescaler register (timx_psc) ? auto - reload register (timx_arr) some timer registers cannot be directly accessed by software, which instead reads and writes a ?buffer register?. the internal registers actually used for timer operations are called ?shadow registers?. the auto - reload register is buffered. writing to or reading from the auto - reload register accesses the buffer register. the contents of the buffer register are transferred into the shadow register permanently or at each update event (uev), depending on the auto - reload buffer enable bit (tim_arbe) in the tim x_cr1 register. the 9 -3 120 - 035x - 000 rev. 1.2 final
EM351 / em357 uev is generated when both the counter reaches the overflow (or underflow when down - counting) and when the tim_udis bit equals 0 in the timx_cr1 register. it can also be generated by software. uev generation is described in detail for e ach configuration. the counter is clocked by the prescaler output ck_cnt, which is enabled only when the counter enable bit (tim_cen) in the timx_cr1 register is set. refer also to the slave mode controller description in the timers a nd external trigger synchronization section to get more details on counter enabling. note that the actual counter enable signal cnt_en is set one clock cycle after tim_cen. note: when the em35x e nters debug mode and the arm ? cortex tm - m3 core is halted, the counters continue to run normally. 9.3.1.1 prescaler the prescaler can divide the counter clock frequency by power of two from 1 through 32768. it is based on a 16- bit counter controlled through the 4 - b it tim_pscexp bit field in the timx_psc register. the factor by which the counter is divided is two raised to the power tim_pscexp (2 tim_pscexp ). it can be changed on the fly as this control register is buffered. the new prescaler ratio is used starting at the next uev . figure 9 - 2 gives an example of the counter behavior when the prescaler ratio is changed on the fly. figure 9 - 2 . counter timing diagram with prescaler division change from 1 to 4 9.3.2 counter modes 9.3.2.1 up - counting mode in up - counting mode, the counter counts from 0 to the auto - reload value (contents of the timx_arr register), then restarts from 0 and generates a counter overflow event. a uev can be generated at each counter overflow, by setting the tim_ug bit in the timx_egr register, or by using the slave mode controller. software can disable the uev by setting the tim_udis bit in the timx_ cr1 register, to avoid updating the shadow registers while writing new values in the buffer registers. no uev will occur until the tim_udis bit is written to 0. both the counter and the prescal e r counter restart from 0, but the prescale rate does not chang e. in addition, if the tim_urs bit in the timx_cr1 register is set, setting the tim_ug bit generates a uev but without setting the int_timuif flag. thus no interrupt request is sent. this avoids generating both update and capture interrupts when clearing t he counter on the capture event. 9 -4 120 - 035x - 000 rev. 1.2 final
EM351 / em357 when a uev occurs, the update flag (the int_timuif bit in the int_timxflag register) is set (unless tim_u rs is 1) and the following registers are updated: ? the buffer of the prescaler is reloaded with the buffer value (conte nts of the timx_psc register). ? the auto - reload shadow register is updated with the buffer value (timx_arr). figure 9 - 3 , figure 9 - 4 , figure 9 - 5 , and figure 9 - 6 show some examples of the counter behavior for different clock frequencies when timx_arr = 0x36. figure 9 - 3 . counter timing diagram, internal c lock d ivided by 1 figure 9 - 4 . counter timing diagram, internal clock divided by 4 figure 9 - 5 . counter timing diagram, update event when tim_arbe = 0 (timx_arr not buffered) 9 -5 120 - 035x - 000 rev. 1.2 final
EM351 / em357 figure 9 - 6 . counter timing diagram, update event when tim_arbe = 1 (timx_arr buffered) 9.3.2.2 down - counting mode in down - counting mode, the counter counts from the auto - reload value (contents of the timx_arr register) down to 0, then restar ts from the auto - reload value and generates a counter underflow event. a uev can be generated at each counter underflow, by setting the tim_ug bit in the timx_egr register, or by using the slave mode controller. software can disable the uev by setting the tim_udis bit in the timx_cr1 register, to avoid updating the shadow registers while writing new values in the buffer registers. no uev occurs until the tim_udis bit is written to 0. however, the counter restarts from the current auto - reload value, whereas the prescal e r?s counter restarts from 0, but the prescale rate doesn?t change. in addition, if the tim_urs bit in the timx_cr1 register is set, setting the tim_ug bit generates a uev , but without setting the int_timuif flag. thus no interrupt request is se nt. this avoids generating both update and capture interrupts when clearing the counter on the capture event. when a uev occurs, the update flag (the int_timuif bit in the int_timxflag register) is set (unless tim_u rs is 1) and the following registers are updated: ? the prescaler shadow register is reloaded with the buffer value (contents of the timx_psc register). ? the auto - reload active register is updated with the buffer value (contents of the timx_arr register). the auto - reload is updated before the counte r is reloaded, so that the next period is the expected one. figure 9 - 7 and figure 9 - 8 show some examples of the counter behavior for different clock frequencies when timx_arr = 0x36. 9 -6 120 - 035x - 000 rev. 1.2 final
EM351 / em357 figure 9 - 7 . counter timing diagram, internal clock divided by 1 figure 9 - 8 . counter timing diagram, internal clock divided by 4 9.3.2.3 center - aligned mode (up/down counting) in center - aligned mode, the counter counts from 0 to the auto - reload value (contents of the timx_arr register) ? 1 and generates a counter overflow event, then counts from the autoreload value down to 1 and generates a counter underflow event. then it restarts counting from 0. in this mode, the direction bit (tim_dir in the timx_cr1 register) cannot be written. it is updated by hardw are and gives the current direction of the counter. the uev can be generated at each counter overflow and at each counter underflow. setting the tim_ug bit in the timx_egr register by software or by using the slave mode controller also generates a uev . in this case, the both the counter and the prescal e r?s counter restart counting from 0. software can disable the uev by setting the tim_udis bit in the timx_cr1 register. this avoids updating the shadow registers while writing new values in the buffer registers. then no uev occurs until the tim_udis bit has been written to 0. however, the counter continues counting up a nd down, based on the current auto - reload value. in addition, if the tim_urs bit in the timx_cr1 register is set, setting the tim_ug bit generates a uev , but without setting the int_timuif flag. thus no interrupt request is sent. this avoids generating bot h update and capture interrupt when clearing the counter on the capture event. when a uev occurs, the update flag (the int_timuif bit in the int_timxflag register) is set (unless tim_u rs is 1) and the following registers are updated: ? the prescaler shadow r egister is reloaded with the buffer value (contents of the timx_psc register). 9 -7 120 - 035x - 000 rev. 1.2 final
EM351 / em357 ? the auto - reload active register is updated with the buffer value (contents of the timx_arr register). if the update source is a counter overflow, the auto - reload is updated befo re the counter is reloaded, so that the next period is the expected one. the counter is loaded with the new value. figure 9 - 9 , figure 9 - 10 , and figure 9 - 11 show some examples of the counter behavior for different clock frequencies. figure 9 - 9 . counter timing diagram, internal clock divided by 1, ti mx_arr = 0x6 figure 9 - 10 . counter timing diagram, update event with tim_arbe = 1 (counter underflow) 9 -8 120 - 035x - 000 rev. 1.2 final
EM351 / em357 figure 9 - 11 . counter timing diagram, update event with tim_arbe = 1 (counter overflow) 9.3.3 clock selection the counter clock can be provided by the following clock sources: ? internal clock (pclk) ? external clock mode 1: external input pin ( tiy ) ? external clock mode 2: external trigger input (etr) ? internal trigger i nput (itr0): using the other timer as prescaler. refer to the section using one timer as prescaler for the other timer for more details. 9.3.3.1 internal clock source (ck_int) the internal clock is selected when the slave mode controller is disabled (tim_sms = 000 in the timx_smcr register). in this mode, the tim_cen , tim_dir (in the timx_cr1 register), and tim_ug bits (in the timx_egr register) are actual control bits and can be changed only by software, except for tim_ug, which remains cleared automatically. as soon as the tim_cen bit is written to 1, the prescaler is clocked by the internal clock ck_int. figure 9 - 12 shows the behavior of the control circuit and the up - counter in normal mode, without prescaling. figure 9 - 12 . control circuit in normal mode, internal clock divided by 1 9.3.3.2 external clock source mode 1 this mode is selected when tim_sms = 111 in the timx_smcr register. the counter can count at each rising or fal ling edge on a selected input. figure 9 - 13 shows the registers an d signals used in the example that follows. 9 -9 120 - 035x - 000 rev. 1.2 final
EM351 / em357 figure 9 - 13 . ti2 external clock connection example for example, to configure the up - counter to count in response to a rising edge on the ti2 input, use the following procedure: ? configure channel 2 to detect rising edges on the ti2 input : w rit e tim_cc2s = 01 in the timx_ccmr1 register. ? configure the input filter duration : write the tim_ic2f bits in the timx_ccmr1 register (if no filter is needed, keep tim_ic2f = 0000). note: the capture prescaler is not used for triggering, so it does not need to be c onfigured. ? select rising edge polarity : write tim_cc2p = 0 in the timx_ccer register. ? configure the timer in external clock mode 1 : write tim_sms = 111 in the timx_smcr register. ? select ti2 as the input source : write tim_ts = 110 in the timx_smcr register. ? enable the counter : write tim_cen = 1 in the timx_cr1 register. when a rising edge occurs on ti2, the counter counts once and the int_timtif flag is set. the delay between the rising edge on ti2 and the actual clock of the counter is due to the resynchro nization circuit on the ti2 input. the relationship between rising edges on ti2 and the resulting counter clocks is shown in figure 9 - 14 . figure 9 - 14 . control circuit in external clock mode 1 9.3.3.3 external clock source mode 2 this mode is selected by writing tim_ece = 1 in the timx_smcr register. the counter can count at each rising or falling edge on the external trigger in put etr. the tim_extrigsel bits in the timx_or register select a clock signal that drives etr, as shown in table 9 - 2 . 9 -10 120 - 035x - 000 rev. 1.2 final
EM351 / em357 table 9 - 2 . tim_extrigsel clock signal selection tim_extrigsel bits clock signal selection 00 pclk (peripheral clock). when running from the 24 mhz crystal oscillator, the pclk frequency is 12 mhz. when the 12 mhz rc oscillator is in use, the frequency is 6 mhz. 01 calibrated 1 khz internal rc oscillator 10 optional 32 .786 khz clock 11 timxclk pin. if the tim_clkmsken bit in the timx_or register is set, this signal is and?ed with the timxmsk pin providing a gated clock input. figure 9 - 15 gives an overview of the external trigger input block. figure 9 - 15 . external t rigger input b lock for exam ple, to configure the up - counter to count each 2 rising edges on etr, use the following procedure: ? as no filter is needed in this example, write tim_etf = 0000 in the timx_smcr register. ? set the prescaler : write tim_etps = 01 in the timx_smcr register. ? sel ect rising edge detection on etr : write tim_etp = 0 in the timx_smcr register. ? enable external clock mode 2 : write tim_ece = 1 in the timx_smcr register. ? enable the counter : write tim_cen = 1 in the timx_cr1 register. the counter counts once each 2 etr ris ing edges. the delay between the rising edge on etr and the actual clock of the counter is due to the resynchronization circuit on the etrp signal. figure 9 - 16 illustrates counting every 2 rising edges of etr using external clock mode 2 . 9 -11 120 - 035x - 000 rev. 1.2 final
EM351 / em357 figure 9 - 16 . control ci rcuit in e xternal c lock m ode 2 9.3.4 capture/compare channels each capture/compare channel is built around a c apture/compare register including a shadow register, an input stage for capture with digital filter, multiplexing and prescaler, and an output stage with comparator and output control. figure 9 - 17 gives an overview of the input stage of one capture/compare channel. the input stage samples the corresponding tiy input to generate a filtered signal (tiyf). then an edge detector with polarity selection generates a signal ( tiyfpy) which can be used either as trigger input by the slave mode controller or as the capture command. it is prescaled before the capture register (icyps). figure 9 - 17 . capture/c ompare channel (e xample: ch annel 1 input s tage) the output stage generates an intermediate reference signal, ocyref, which is only used internally. ocyref is always active high, but it may be inverted to create the output signal, ocy, that controls a gpio output. figure 9 - 18 shows the basic elements of a capture/compare channel . 9 -12 120 - 035x - 000 rev. 1.2 final
EM351 / em357 figure 9 - 18 . capture/compare channel 1 main circuit figure 9 - 19 show details of the output stage of a c apture/compare channel . figure 9 - 19 . output stage of capture/compare channel (channel 1) the capture/compare block is made of a buffer register and a shadow register. writes and reads always access the buffer register. in capture mode, captures are first written to the shadow register, then copied into the buffer register. in compare mode, the con tent of the buffer register is copied into the shadow register which is compared to the counter. 9.3.5 input capture mode in input capture mode, a capture/compare register (timx_ccry) latches the value of the counter after a transition is detected by the corresp onding icy signal. when a capture occurs, the corresponding int_timccyif flag in the int_timxflag register is set, and an interrupt request is sent if enabled. 9 -13 120 - 035x - 000 rev. 1.2 final
EM351 / em357 if a capture occurs when the int_timccyif flag is already high, then the missed capture flag in t_timmissccyif in the int_timxmiss register is set. int_timccyif can be cleared by software writing a 1 to its bit or reading the captured data stored in the timx_ccry register. to clear the int_timmissccyif bit, write a 1 to it. the following example sho ws how to capture the counter value in the timx_ccr1 when the ti1 input rises. ? select the active input: timx_ccr1 must be linked to the ti1 input, so write the tim_cc1s bits to 01 in the timx_ccmr1 register. as soon as tim_cc1s becomes different from 00, the channel is configured in input and the timx_ccr1 register becomes read - only. ? program the required input filter duration with respect to the signal connected to the timer, when the input is one of the tiy (icyf bits in the timx_ccmr1 register). consider a situation in which, when toggling, the input signal is unstable during at most 5 internal clock cycles. the filter duration must be longer than these 5 clock cycles. the transition on ti1 can be validated when 8 consecutive samples with the new level ha ve been detected (sampled at pclk frequency). to do this, write the tim_ic1f bits to 0011 in the timx_ccmr1 register. ? select the edge of the active transition on the ti1 channel : write the tim_cc1p bit to 0 in the timx_ccer register (rising edge in this ca se). ? program the input prescaler: in this example, the capture is to be performed at each valid transition, so the prescaler is disabled (write the tim_ic1ps c bits to 00 in the timx_ccmr1 register). ? enable capture from the counter into the capture register : set the tim_cc1e bit in the timx_ccer register. ? if needed, enable the related interrupt request by setting the int_timcc1if bit in the int_timxcfg register. ? when an input capture occurs: ? the timx_ccr1 register gets the value of the counter on the active transition. ? int_timcc1if flag is set (capture/compare interrupt flag). the missed capture/compare flag int_timmisscc1if in int_timxmiss is also set if another capture occurs before the int_timcc1if flag is cleared. ? an interrupt may be generated if enabled by the int_timcc1if bit. to detect missed captures reliably, read captured data in timxccry before checking the missed capture/compare flag. this sequence avoids missing a capture that could happen after reading the flag and before reading the data. note: soft ware can generate ic interrupt requests by setting the corresponding tim_ccyg bit in the timx_egr register. 9.3.6 pwm input mode this mode is a particular case of input capture mode. the procedure is the same except: ? two icy signals are mapped on the same tiy in put. ? these two icy signals are active on edges with opposite polarity. ? one of the two tiyfp signals is selected as trigger input and the slave mode controller is configured in reset mode. for example, to measure the period in the timx_ccr1 register and the duty cycle in the timx_ccr2 register of the pwm applied on ti1, use the following procedure depending on ck_int frequency and prescaler value: ? select the active input for timx_ccr1: write the tim_cc1s bits to 01 in the timx_ccmr1 register (ti1 selected). ? select the active polarity for ti1fp1, used both for capture in the timx_ccr1 and counter clear, by writing the tim_cc1p bit to 0 (active on rising edge). 9 -14 120 - 035x - 000 rev. 1.2 final
EM351 / em357 ? select the active input for timx_ ccr2by writing the tim_cc2s bits to 10 in the timx_ccmr1 register (ti1 selected). ? select the active polarity for ti1fp2 (used for capture in the timx_ccr2) by writing the tim_cc2p bit to 1 (active on falling edge). ? select the valid trigger input by writing the tim_ts bits to 101 in the timx_smcr register (ti1fp1 selected). ? configure the slave mode controller in reset mode by writing the tim_sms bits to 100 in the timx_smcr register. ? enable the captures by writing the tim_cc1e and tim_cc2e bits to 1 in the t imx_ccer register. figure 9 - 20 illustrates t his example . figure 9 - 20 . pwm i nput mode t iming 9.3.7 forced output mode in ou tput mode (ccys bits = 00 in the timx_ccmr1 register), software can force each output compare signal (ocyref and then ocy) to an active or inactive level independently of any comparison between the output compare register and the counter. to force an outpu t compare signal (ocyref/ocy) to its active level, write 101 in the tim_ocym bits in the corresponding timx_ccmr1 register. ocyref is forced high (ocyref is always active high) and ocy gets the opposite value to the tim_ccyp polarity bit. for example, tim_ ccyp = 0 defines ocy as active high, so when ocyref is active, ocy is also set to a high level. the ocyref signal can be forced low by writing the tim_ocym bits to 100 in the timx_ccmr1 register. the comparison between the timx_ccry shadow register and th e counter is still performed and allows the int_timxccryif flag to be set. interrupt requests can be sent accordingly. this is described in the output compare mode section. 9.3.8 output compare mode this mode is used to control an output waveform or to indicate when a period of time has elapsed. when a match is found between the capture/compare register and the counter, the output compare function: ? assigns the corresponding output pin to a programmable value defined by the output compare mode (the tim_ocym bits i n the timx_ccmr1 register) and the output polarity (the tim_ccyp bit in the timx_ccer register). the output can be frozen (tim_ocym = 000), be set active (tim_ocym = 001), be set inactive (tim_ocym = 010), or can toggle (tim_ocym = 011) on the match. 9 -15 120 - 035x - 000 rev. 1.2 final
EM351 / em357 ? sets a flag in the interrupt flag register (the int_timccyif bit in the int_timxflag register). ? generates an interrupt if the corresponding interrupt mask is set (the tim_ccyif bit in the int_timxcfg register). the timx_ccry registers can be programmed with or without buffer registers using the tim_ocy be bit in the timx_ccmr1 register. in output compare mode, the uev has no effect on ocyref or the ocy output. the timing resolution is one count of the counter. output compare m ode can also be used to output a single pulse (in one pulse mode). procedure: 1. select the counter clock (internal, external, and prescaler). 2. write the desired data in the timx_arr and timx_ccry registers. 3. set the int_timccyif bit in int_timxcfg if an interr upt request is to be generated. 4. select the output mode. for example, you must write tim_ocym = 011, tim_ocy be = 0, tim_ccyp = 0 and tim_ccye = 1 to toggle the ocy output pin when timx_cnt matches timx_ccry, timx_ccry buffer is not used, ocy is enabled and active high. 5. enable the counter : set the tim_cen bit in the timx_cr1 register. to control the output waveform, software can update the timx_ccry register at any time, provided that the buffer register is not enabled (tim_ocy be = 0). otherwise timx_ccry sh adow register is updated only at the next uev . an example is given in figure 9 - 21 . figure 9 - 21 . output compare mode, t oggle on oc1 9.3.9 pwm mode pulse width modulation mode allows you to generate a signal with a frequency determ ined by the value of the timx_arr register, and a duty cycle determined by the value of the timx_ccry register. pwm mode can be selected independently on each channel (one pwm per ocy output) by writing 110 (pwm mode 1) or 111 (pwm mode 2) in the tim_ocym bits in the timx_ccmr1 register. the corresponding buffer register must be enabled by setting the tim_ocy be bit in the timx_ccmr1 register. finally, in up - counting or center - aligned mode the auto - reload buffer register must be enabled by setting the tim_ar be bit in the timx_cr1 register. 9 -16 120 - 035x - 000 rev. 1.2 final
EM351 / em357 because the buffer registers are only transferred to the shadow registers when a uev occurs, before starting the counter initialize all the registers by setting the tim_ug bit in the timx_egr register. ocy polarity is softw are programmable using the tim_ccyp bit in the timx_ccer register. it can be programmed as active high or active low. ocy output is enabled by the tim_ccye bit in the timx_ccer register. refer to the timx_ccer register description in the registers section for more details. in pwm mode (1 or 2), timx_cnt and timx_ccry are always compared to determine whether timx_ccry timx_cnt or timx_cnt timx_ccry, depending on the direction of the counter. the ocyref signal is asserted only: ? when the result of the comparison changes, or ? when the output compare mode (tim_ocym bits in the timx_ccmr1 register) switches from the ?frozen? configuration (no comparison, tim_ocym = 000) to one of the pwm modes (tim_ocym = 110 or 111). this allows software to force a pwm output to a particular state while the timer is running. the timer is able to generate pwm in edge - aligned mode or center - aligned mode depending on the tim_cms bits in the t imx_cr1 register. 9.3.9.1 pwm edge - aligned mode: up - c ounting c onfiguration up - counting is active when the tim_dir bit in the timx_cr1 register is low. refer to the section up - counting mode . the following example uses pwm mode 1. the reference pwm signal ocyref is high as long as timx_cnt < timx_ccry, otherwise it becomes low. if the compare value in timx_ccry is greater than the auto - reload value in timx_arr, then ocyref is held at 1. if the compare value is 0, then ocyref is held at 0. figure 9 - 22 shows some edge - aligned pwm waveforms in an example, where timx_arr = 8. figure 9 - 22 . edge - aligned pwm w aveforms (arr = 8) 9.3.9.2 pwm edge - aligned mode: down - c ount ing c onfiguration down - counting is active when the tim_dir bit in the tim x_cr1 register is high. refer to the down - counting mode section for more information . in pwm mode 1, the reference signal ocyref is low as long as timx_cnt > timx_ccry , otherwise it becomes high. if the compare value in timx_ccry is greater than the auto - reload value in timx_arr, then ocyref is held at 1. zero - percent pwm is not possible in this mode. 9 -17 120 - 035x - 000 rev. 1.2 final
EM351 / em357 9.3.9.3 pwm center - aligned mode center - aligned mode is active except when the tim_cms bits in the timx_cr1 register are 00 (all configurations where tim_cms is non - zero have the same effect on the ocyref/ocy signals). the compare flag is set when the counter counts up, when it counts down, or when it counts up and down, depending o n the tim_cms bits configuration. the direction bit (tim_dir) in the timx_cr1 register is updated by hardware and must not be changed by software. refer to the center - aligned mode (up/down counting) section for more information. figure 9 - 23 shows some center - aligned pwm waveforms in an example where : ? timx_arr = 8 ? pwm mode is the pwm mode 1 ? the output compare flag is set when the counter counts down corresponding to the center - aligned mode 1 selected for tim_cms = 01 in the timx_cr1 register figure 9 - 23 . center - aligned pwm waveforms (arr = 8) 9 -18 120 - 035x - 000 rev. 1.2 final
EM351 / em357 hints on using center - aligned mode: ? when starting in center - aligned mode, the current up - down configuration is used. this means that the counter counts up or down depending on the value written in the tim_dir bit i n the timx_cr1 register. the tim_dir and tim_cms bits must not be changed at the same time by the software. ? writing to the counter while running in center - aligned mode is not recommended as it can lead to unexpected results. in particular: ? the direction is not updated when the value written to the counter that is greater than the auto - reload value (timx_cnt > timx_arr). for example, if the counter was counting up, it continues to count up. ? the direction is updated when 0 or the timx_arr value is written to the counter, but no uev is generated. ? the safest way to use center - aligned mode is to generate an update by software (setting the tim_ug bit in the timx_egr register) just before starting the counter, and not to write the counter while it is running. 9.3.10 one -p ulse mode one - pulse mode (opm) is a special case of the previous modes. it allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. starting the counter can be controlled through the slave mode controller. generating the waveform can be done in output compare mode or pwm mode. select opm by setting the tim_opm bit in the timx_cr1 register. this makes the counter stop automatically at t he next uev . a pulse can be correctly generated only if the compare value is different from the counter initial value. before starting (when the timer is waiting for the trigger), the configuration must be: in up - counting: timx_cnt < timx_ccry ? timx_ a rr ( in particular, 0 < timx_ccry), in down - counting: timx_cnt > timx_ccry. for example, to generate a positive pulse on oc1 with a length of t pulse and after a delay of t delay as soon as a rising edge is detected on the ti2 input pin, using ti2fp2 as trigger 1 : ? map ti2fp2 on ti2 : write tim_ic2s = 01 in the timx_ccmr1 register. ? ti2fp2 must detect a rising edge. write tim_cc2p = 0 in the timx_ccer register. ? configure ti2fp2 as trigger for the slave mode controller (trgi) : write tim_ts = 110 in the timx_smcr register. ? use ti2fp2 to start the counter : write tim_sms to 110 in the timx_smcr register (trigger mode). ? the opm waveform is defined : write the compare registers , taking into account the clock frequency and the counter prescaler. ? the t delay is defined b y the value written in the timx_ccr1 register. ? the t pulse is defined by the difference between the auto - reload value and the compare value (timx_arr - timx_ccr1). ? to build a waveform with a transition from 0 to 1 when a compare match occurs and a transiti on from 1 to 0 when the counter reaches the auto - reload value : ? e nable pwm mode 2 : write tim_oc1m = 111 in the timx_ccmr1 register. ? optionally, enable the buffer registers : write tim_oc1 be = 1 in the timx_ccmr1 register and tim_arbe in the timx_cr1 registe r. in this case, also write the compare value in the timx_ccr1 register, the auto - reload value in the timx_arr register, generate an update by setting the tim_ug bit, and wait for external trigger event on ti2. tim_cc1p is written to 0 in this example. in the example, the tim_dir and tim_cms bits in the timx_cr1 register should be low. since only one pulse is desired, software should set the tim_opm bit in the timx_cr1 register to stop the counter at the next uev (when the counter rolls over from the auto - r eload value back to 0). 9 -19 120 - 035x - 000 rev. 1.2 final
EM351 / em357 figure 9 - 24 illustrates this example . figure 9 - 24 . example of one pulse mode 9.3.10.1 a special case: ocy fast enable in one - pulse mode, the edge detection on the tiy input sets the tim_cen bit, which enables the counter. then the comparison between the counter and the compare value toggles the output. however, several clock cycles are needed for this oper ation, and it limits the minimum delay (t delay min) achievable. to output a waveform with the minimum delay, set the tim_ocyfe bit in the timx_ccmr1 register. then ocyref and ocy are forced in response to the stimulus, without taking the comparison into ac count. its new level is the same as if a compare match had occurred. tim_ocyfe acts only if the channel is configured in pwm mode 1 or 2. 9.3.11 encoder interface mode to select encoder interface mode, write tim_sms = 001 in the timx_smcr register to count only ti2 edges, tim_sms = 010 to count only ti1 edges, and tim_sms = 011 to count both ti1 and ti2 edges. select the ti1 and ti2 polarity by programming the tim_cc1p and tim_cc2p bits in the timx_ccer register. if needed, program the inp ut filter as well. the two inputs ti1 and ti2 are used to interface to an incremental encoder (see table 9 - 3 ). assuming that it is enabled (the tim_cen bit in the tim x_cr1 register = 1) , the counter is clocked by each valid transition on ti1fp1 or ti2fp2 (ti1 and ti2 after input filter and polarity selection, ti1fp1 = ti1 if not filtered and not inverted, ti2fp2 = ti2 if not filtered and not inverted.) the timer input logic evaluates the sequence of the two inputs? values, and from this generates both count pulses and the direction signal. depending on the sequence, the counter counts up or down, and hardware modifies the tim_dir bit in the timx_cr1 register accordingly . the tim_dir bit is calculated at each transition on any input (ti1 or ti2), whether the counter is counting on ti1 only, ti2 only, or both ti1 and ti2. encoder interface mode acts simply as an external clock with direction selection. this means that the counter counts continuously between 0 and the auto - reload value in the timx_arr register (0 to timx_arr or timx_arr down to 0 depending on the direction), so timx_arr must be configured before starting. in the same way, the capture, compare, prescaler, and trigger output features continue to work as normal. in this mode the counter is modified automatically following the speed and the direction of the incremental encoder, and therefore its contents always represent the encoder?s position. the count directio n corresponds to the rotation direction of the connected sensor. table 9 - 3 summarizes the possible combinations, assuming ti1 and ti2 do not switch at the same time. 9 -20 120 - 035x - 000 rev. 1.2 final
EM351 / em357 table 9 - 3 . counting direction versus encoder signals active edge s level on opposite signal (ti1fp1 for ti2, ti2fp2 for ti1) ti1fp1 signal ti2fp2 signal rising falling rising falling counting on ti1 only high down up no count no count low up down no count no count counting on ti2 only high no count no count up down low no count no count down up counting on ti1 and ti2 high down up up down low up down down up an external incremental encoder can be connected directly to the mcu without external interface logic. however, comparators are normally used to convert an encoder?s differential outputs to digital signals, and this greatly increases noise immunity. if a third encoder output indicates the mech anical zero (or index) position, it may be connected to an external interrupt input and can trigger a counter reset. figure 9 - 25 gives an example of counter operation , showing count signal generation and direction control. it also shows how input jitter is compensated for when both inputs are used for counting. this might occur if the sensor is positioned near one of the switching points. this example assumes the follo wing configuration: ? tim_cc1s = 01 (timx_ccmr1 register, ic1fp1 mapped on ti1). ? tim_cc2s = 01 (timx_ccmr2 register, ic2fp2 mapped on ti2). ? tim_cc1p = 0 (timx_ccer register, ic1fp1 non - inverted, ic1fp1 = ti1). ? tim_cc2p = 0 (timx_ccer register, ic2fp2 non - inv erted, ic2fp2 = ti2). ? tim_sms = 011 (timx_smcr register, both inputs are active on both rising and falling edges). ? tim_cen = 1 (timx_cr1 register, counter is enabled). figure 9 - 25 . example of counter ope ratio n in encoder interface mode 9 -21 120 - 035x - 000 rev. 1.2 final
EM351 / em357 figure 9 - 26 gives an example of counter behavior when ic1fp1 polarity is inverted (same configuration as above except tim_cc1p = 1). figure 9 - 26 . example o f encoder interface mode with ic1fp1 polarity inverted the timer configured in encoder interface mode provides information on a sensor?s current position. to obtain dynamic information (speed, acceleration/deceleration), measure the period between two en coder events using a second timer configured in capture mode. the output of the encoder that indicates the mechanical zero can be used for this purpose. depending on the time between two events, the counter can also be read at regular times. do this by lat ching the counter value into a third input capture register. (in this case the capture signal must be periodic and can be generated by another timer). 9.3.12 timer input xor function the tim_ti1s bit in the tim1_cr2 register allows the input filter of channel 1 t o be connected to the output of a xor gate that combines the three input pins timxc2 to timxc4. the xor output can be used with all the timer input functions such as trigger or input capture. it is especially useful to interface to hall effect sensors. 9.3.13 ti mers and external trigger synchronization the timers can be synchronized with an external trigger in several modes: reset mode, gated mode, and trigger mode. 9.3.13.1 slave mode: reset mode reset mode reinitializes the counter and its prescaler in response to an ev ent on a trigger input. moreover, if the tim_urs bit in the timx_cr1 register is low, a uev is generated. then all the buffered registers (timx_arr, timx_ccry) are updated. in the following example, the up - counter is cleared in response to a rising edge on the ti1 input: ? configure the channel 1 to detect rising edges on ti1: ? configure the input filter duration. in this example, no filter is required so tim_ic1f = 0000. ? the capture prescaler is not used for triggering, so it is not configured. ? the tim_cc1 s bits select the input capture source only, tim_cc1s = 01 in the timx_ccmr1 register. ? write tim_cc1p = 0 in the timx_ccer register to validate the polarity, and detect rising edges only. ? configure the timer in reset mode : write tim_sms = 100 in the timx_ smcr register. ? select ti1 as the input source by writing tim_ts = 101 in the timx_smcr register. ? start the counter : write tim_cen = 1 in the timx_cr1 register. 9 -22 120 - 035x - 000 rev. 1.2 final
EM351 / em357 the counter starts counting on the internal clock, then behaves normally until the ti1 rising edge. when ti1 rises, the counter is cleared and restarts from 0. in the meantime, the trigger flag is set (the int_timtif bit in the int_timxflag register) and a n interrupt request can be sent if enabled (depending on the int_timtif bit in the int_timxcfg register). figure 9 - 27 shows this behavior when the auto - reload register timx_arr = 0x36. the delay between the rising edge on ti1 and the actual reset of the counter is due to the resynchronization circuit on the ti1 input. figure 9 - 27 . control circuit in reset m ode 9.3.13.2 slave mode: gated mode in gated mode the counter is enabled depending on the level of a selected input. in the following example, the up - counter counts only when the ti1 input is low: ? configure channel 1 to detect low levels on ti1 : ? configure the input filter d uration. in this example, no filter is required, so tim_ic1f = 0000. ? the capture prescaler is not used for triggering, so it is not configured. ? the tim_cc1s bits select the input capture source only, tim_cc1s = 01 in the timx_ccmr1 register. ? write tim_c c1p = 1 in the timx_ccer register to validate the polarity (and detect low level only). ? configure the timer in gated mode : write tim_sms = 101 in the timx_smcr register. ? select ti1 as the input source by writing tim_ts = 101 in the timx_smcr register. ? ena ble the counter : write tim_cen = 1 in the timx_cr1 register. in gated mode, the counter does not start if tim_cen = 0, regardless of the trigger input level. the counter starts counting on the internal clock as long as ti1 is low and stops as soon as ti1 becomes high. the int_timtif flag in the int_timxflag register is set when the counter starts and when it stops. the delay between the rising edge on ti1 and the actual stop of the counter is due to the resynchronization circuit on the ti1 input. figure 9 - 28 shows the counter in gated mode with counting enabled when ti1 is low. figure 9 - 28 . control circuit in gated mode 9 -23 120 - 035x - 000 rev. 1.2 final
EM351 / em357 9.3.13.3 slave mode: trigger mode in trigger mode the counter starts in response to an event on a selected input. in the following example, the up - counter starts in response to a rising edge on the ti2 input: ? configure channel 2 to detect rising edges on ti2 : ? con figure the input filter duration. in this example, no filter is required so tim_ic2f = 0000. ? the capture prescaler is not used for triggering, so it is not configured. ? the tim_cc2s bits select the input capture source only, tim_cc2s = 01 in the timx_ccmr 1 register. ? write tim_cc2p = 0 in the timx_ccer register to validate the polarity and detect high level only. ? configure the timer in trigger mode : write tim_sms = 110 in the timx_smcr register. ? select ti2 as the input source by writing tim_ts = 110 in the timx_smcr register. when a rising edge occurs on ti2, the counter starts counting on the internal clock and the int_timtif flag is set. the delay between the rising edge on ti2 and the actual s tart of the counter is due to the resynchronization circuit on the ti2 input. figure 9 - 29 illustrates the example in which the counter is started by a rising edge on t i2. figure 9 - 29 . control circuit in trigger mod e 9.3.13.4 slave mode: external clock mode 2 +trigger mode external clock mode 2 can be used in combination with another slave mode (except external clock mode 1 and encoder mode). in this case, the etr signal is used as external clock input, and another input can be selected as trigger input when operating in res et mode, gated mode or trigger mode. it is not recommended to select etr as trgi through the tim_ts bits of timx_smcr register. in the following example, shown in figure 9 - 30, the up - counter is incremented at each rising edge of the etr signal as soon as a rising edge of ti1 occurs: ? configure the external trigger input circuit : program the timx_smcr register as follows: ? tim_etf = 0000: no filter. ? tim_etps = 00: prescal er disabled. ? tim_etp = 0: detection of rising edges on etr and tim_ece = 1 to enable the external clock mode 2. ? configure the channel 1 to detect rising edges on ti , as follows : ? tim_ic1f = 0000: no filter. ? the capture prescaler is not used for triggering a nd does not need to be configured. ? tim_cc1s = 01 in the timx_ccmr1 register to select only the input capture source. ? tim_cc1p = 0 in the timx_ccer register to validate the polarity (and detect rising edge only). ? configure the timer in trigger mode : write ti m_sms = 110 in the timx_smcr register. ? select ti1 as the input source by writing tim_ts = 101 in the timx_smcr register. 9 -24 120 - 035x - 000 rev. 1.2 final
EM351 / em357 a rising edge on ti1 enables the counter and sets the int_timtif flag. the counter then counts on etr rising edges. the delay between the rising edge of the etr signal and the actual reset of the counter is due to the resynchronization circuit on etrp input. figure 9 - 30 . control circuit in external clock mode 2 + trigger mode 9.3.14 timer synch ronization the two timers can be linked together internally for timer synchronization or chaining. a timer configured in master mode can reset, start, stop or clock the counter of the other timer configured in slave mode. figure 9 - 31 presents an overview of the trigger selection and the master mode selection blocks. 9.3.14.1 using one timer as prescaler for the other timer for example, to configure timer 1 to act as a prescaler for timer 2: ? configure timer 1 in master mode so that it outputs a periodic trigger signal on each uev . writing tim_mms = 010 in the tim1_cr2 register causes a rising edge to be output on trgo each time a uev is generated. ? to connect the trgo output of ti mer 1 to timer 2, configure timer 2 in slave mode using itr0 as an internal trigger. write tim_ts = 100 in the tim2_smcr register. ? put the slave mode controller in external clock mode 1 : w rite tim_sms = 111 in the tim2_smcr register. this causes timer 2 to be clocked by the rising edge of the periodic timer 1 trigger signal , which corresponds to the timer 1 counter overflow. ? finally , enable both timers : set their respective tim_cen bits in the timx_cr1 register. note: if ocy is selected on timer 1 as trigger ou tput (tim_mms = 1xx), its rising edge is used to clock the counter of timer 2. figure 9 - 31 . master/slave timer example 9 -25 120 - 035x - 000 rev. 1.2 final
EM351 / em357 9.3.14.2 using one timer to enable the other timer in this example, shown in figure 9 - 32, the enable of timer 2 is controlled with the output compare 1 of timer 1. timer 2 counts on the divided internal clock only when oc1ref of timer 1 is high. both counter clo ck frequencies are divided by 3 by the prescaler compared to ck_int (f ck_cnt = f ck_int /3). ? configure timer 1 in master mode to send its output compare reference (oc1ref) signal as trigger output : write tim_mms = 100 in the tim1_cr2 register. ? configure the timer 1 oc1ref waveform (tim1_ccmr1 register). ? configure timer 2 to get the input trigger from timer 1 : write tim_ts = 000 in the tim2_smcr register. ? configure timer 2 in gated mode : write tim_sms = 101 in the tim2_smcr register. ? enable timer 2 : write 1 i n the tim_cen bit in the tim2_cr1 register. ? start timer 1 : write 1 in the tim_cen bit in the tim1_cr1 register. note: the counter 2 clock is not synchronized with counter 1, this mode only affects the timer 2 counter enable signal. figure 9 - 32 . gating timer 2 with oc1ref of timer 1 in the example in figure 9 - 32 , the timer 2 counter and prescaler are not initialized before bei ng started. so they start counting from their current value. it is possible to start from a given value by resetting both timers before starting timer 1, then writing the desired value in the timer counters. the timers can easily be reset by software using the tim_ug bit in the timx_egr registers. the next example, illustrated in figure 9 - 33 , synchronizes timer 1 and timer 2. timer 1 is the master and starts from 0. tim er 2 is the slave and starts from 0xe7. the prescaler ratio is the same for both timers. timer 2 stops when timer 1 is disabled by writing 0 to the tim_cen bit in the tim1_cr1 register: ? configure timer 1 in master mode to send its output compare reference (oc1ref) signal as trigger output : write tim_mms = 100 in the tim1_cr2 register) ? configure the timer 1 oc1ref waveform (tim1_ccmr1 register). ? configure timer 2 to get the input trigger from timer 1 : write tim_ts = 000 in the tim2_smcr register. ? configure timer 2 in gated mode : write tim_sms = 101 in the tim2_smcr register. ? reset timer 1 : write 1 in the tim_ug bit (tim1_egr register. ? reset timer 2 by writing 1 in the tim_ug bit (tim2_egr register). ? initialize timer 2 to 0xe7 : write 0xe7 in the timer 2 counter (tim2_cntl). ? enable timer 2 : write 1 in the tim_cen bit in the tim2_cr1 register. ? start timer 1 : write 1 in the tim_cen bit in the tim1_cr1 register. ? stop timer 1 : write 0 in the tim_cen bit in the tim1_cr1 register. 9 -26 120 - 035x - 000 rev. 1.2 final
EM351 / em357 figure 9 - 33 . gating timer 2 with enable of timer 1 9.3.14.3 using one timer to start the other timer in this example (see figure 9 - 34 ), the enable of timer 2 is set with the uev of timer 1. timer 2 starts counting from its current value (which can be non - zero) on the divided internal clock as soon as timer 1 generates the uev . when timer 2 receives the trigger signal its tim_cen bit is au tomatically set and the counter counts until 0 is written to the tim_cen bit in the tim2_cr1 register. both counter clock frequencies are divided by 3 by the prescaler compared to ck_int (f ck_cnt = f ck_int /3). ? configure timer 1 in master mode to send its u ev as trigger output : write tim_mms = 010 in the tim1_cr2 register. ? configure the timer 1 period (tim1_arr register). ? configure timer 2 to get the input trigger from timer 1 : write tim_ts = 000 in the tim2_smcr register. ? configure timer 2 in trigger mode . w rite tim_sms = 110 in the tim2_smcr register. ? start timer 1: write 1 in the tim_cen bit in the tim1_cr1 register. figure 9 - 34 . triggering timer 2 with update of timer 1 as in the previous example, both counters can be initialized before starting counting. figure 9 - 35 shows the behavior with the same configuration shown in figure 9 - 34 , but in trigger mode instead of gated mode (tim_sms = 110 in the tim2_smcr register). 9 -27 120 - 035x - 000 rev. 1.2 final
EM351 / em357 figure 9 - 35 . triggering timer 2 with enable of timer 1 9.3.14.4 starting both timers synchronously in response to an external trigger this example sets the enable of timer 1 when its ti1 input rises, and the enable of timer 2 with the enable of timer 1. to ensure the counters are aligned, time r 1 must be configured in master/slave mode (slave with respect to ti1, master with respect to timer 2): ? configure timer 1 in master mode to send its enable as trigger output : write tim_mms = 001 in the tim1_cr2 register. ? configure timer 1 slave mode to get the input trigger from ti1 : write tim_ts = 100 in the tim1_smcr register. ? configure timer 1 in trigger mode : write tim_sms = 110 in the tim1_smcr register. ? configure the timer 1 in master/slave mode : write tim_msm = 1 in the tim1_smcr register. ? configu re timer 2 to get the input trigger from timer 1 : write tim_ts = 000 in the tim2_smcr register. ? configure timer 2 in trigger mode : write tim_sms = 110 in the tim2_smcr register. when a rising edge occurs on ti1 (timer 1), both counters start counting synch ronously on the internal clock and both timers? int_timtif flags are set. figure 9 - 36 shows this in operation. note: in this example both timers are initialized before starting by setting their respective tim_ug bits. both counters starts from 0, but an offset can be inserted between them by writing any of the counter registers (timx_cnt). the master/slave mode inserts a delay between cnt_en and ck_psc on timer 1. 9 -28 120 - 035x - 000 rev. 1.2 final
EM351 / em357 figure 9 - 36 . triggering timer 1 and 2 with timer 1 ti1 input 9.3.15 timer signal descriptions table 9 - 4 . timer signal descriptions signal internal/ external description ck_int internal internal clock source: connects to em35x peripheral clock (pclk) in internal clock mode. ck_psc internal input to the clock prescaler. etr internal external trigger input (used in external timer mode 2): a clock selected by tim_extrigsel in timx_or. etrf internal external trigger: etrp after filtering. etrp internal external trigger: etr after polarity selection, edge detection and prescaling. icy external input capture or clock: tiy after filtering and edge detection. icyps internal input capture signal after filtering, edge detection and prescaling: input to the capture register. itr0 internal internal trigger input: connected to the other timer ?s output, trgo. ocy external output compare: timxcy when used as an output. same as ocyref but includes possible polarity inversion. ocyref internal output compare reference: always active high, but may be inverted to produce ocy. pclk external peripheral clock connects to ck_int and used to clock input filtering. its frequency is 12 mhz if using the 24 mhz crystal oscillator and 6 m h z if using the 12 mhz rc oscillator. tiy internal timer input: timxcy when used as a timer input. tiyfpy internal timer input after filtering and polarity selection. timxcy internal timer channel at a gpio pin: can be a capture input (icy) or a compare output (ocy). timxclk external clock input (if selected) to the external trigger signal (etr). timxmsk ex ternal clock mask (if enabled) and?ed with the other timer?s timxclk signal. trgi internal trigger input for slave mode controller. 9 -29 120 - 035x - 000 rev. 1.2 final
EM351 / em357 9.4 interrupts each timer has its own top - level nvic interrupt . writing 1 to the int_timx bit in the int_cfgset register enables the timx interrupt, and writing 1 to the int_timx bit in the int_cfgclr register disables it . chapter 11, interrupt system d escribes the interrupt system in detail. several kinds of timer events can generate a timer interrupt, and each has a status flag in the int_timxflag register to identify the reason(s) for the interrupt: ? int_timtif ? set by a rising edge on an external trigger, either edge in gated mode ? int_timccryif ? set by a channel y input capture or output c ompare event ? int_timuif ? set by a uev clear bits in int_timxflag by writing a 1 to their bit position. when a channel is in capture mode, reading the timx_ccry register will also clear the int_timccryif bit. the int_timxcfg register controls whether or not the int_timxflag bits actually request a top - level nvic timer interrupt. only the events whose bits are set to 1 in int_timxcfg can do so. if an input capture or output compare event occurs and its int_timmissccyif is alre ady set, the corresponding capture/compare missed flag is set in the int_tmrxmiss register. clear a bit in the int_tmrxmiss register by writing a 1 to it. 9 -30 120 - 035x - 000 rev. 1.2 final
EM351 / em357 9.5 registers timx_cr1 tim1_cr1 timer 1 control register 1 address: 0x4000e000 reset: 0x0 tim2_cr1 timer 2 control register 1 address: 0x4000f000 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 tim_arbe tim_cms tim_dir tim_opm tim_urs tim_udis tim_cen bitname bitfield access description tim_arbe [7] rw auto - reload buffer enable. 0: timx_arr register is not buffered. 1: timx_arr register is buffered. tim_cms [6:5] rw center - aligned mode selection. 00: edge - aligned mode. the counter counts up or down depending on the direction bit (tim_dir). 01: center - aligned mode 1. the counter counts up and down alternatively. output compare interrupt flags of configured output channels (tim_ccys=00 in timx_ccmry register) are set only when the cou nter is counting down. 10: center - aligned mode 2. the counter counts up and down alternatively. output compare interrupt flags of configured output channels (tim_ccys=00 in timx_ccmry register) are set only when the counter is counting up. 11: center - align ed mode 3. the counter counts up and down alternatively. output compare interrupt flags of configured output channels (tim_ccys=00 in timx_ccmry register) are set both when the counter is counting up or down. note: software may not switch from edge - aligne d mode to center - aligned mode when the counter is enabled (tim_cen=1). tim_dir [4] rw direction. 0: counter used as up - counter. 1: counter used as down - c o u n t e r. tim_opm [3] rw one pulse mode. 0: counter does not stop counting at the next uev . 1: counter stops counting at the next uev (and clears the bit tim_cen). tim_urs [2] rw update request source. 0: when enabled, update interrupt requests are sent as soon as registers are updated (counter overflow/underflow, setting the tim_ug bit, or upda te generation through the slave mode controller). 1: when enabled, update interrupt requests are sent only when the counter reaches overflow or underflow. tim_udis [1] rw update disable. 0: a ue v is generated as soon as a counter overflow occurs, a softwa re update is generated, or a hardware reset is generated by the slave mode controller. shadow registers are then loaded with their buffer register values. 1: a ue v is not generated and shadow registers keep their value (timx_arr, timx_psc, timx_ccry ). the counter and the prescaler are reinitialized if the tim_ug bit is set or if a hardware reset is received from the slave mode controller. 9 -31 120 - 035x - 000 rev. 1.2 final
EM351 / em357 bitname bitfield access description tim_cen [0] rw counter enable. 0: counter disabled. 1: counter enabled. note: external clock, gated mode and en coder mode can work only if the tim_cen bit has been previously set by software. trigger mode sets the tim_cen bit automatically through hardware. 9 -32 120 - 035x - 000 rev. 1.2 final
EM351 / em357 timx_cr2 tim1_cr2 timer 1 control register 2 address: 0x4000e004 reset: 0x0 tim2_cr2 timer 2 control regis ter 2 address: 0x4000f004 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 tim_ti1s tim_mms 0 0 0 0 bitname bitfield access description tim_ti1s [7] rw ti1 selection. 0: ti1m (input of the digital filter) is connected to ti1 input. 1: ti1m is connected to the ti_hall inputs (xor combination). tim_mms [6:4] rw master mode selection. this selects the information to be sent in master mode to a slave timer for synchronization using the trigger output (trgo). 000: reset - the tim_ug bit in the tmrx_egr register is trigger output. if the reset is generated by the trigger input (slave mode controller configured in reset mode), then the signal on trgo is d elayed compared to the actual reset. 001: enable - counter enable signal cnt_en is trigger output. this mode is used to start both timers at the same time or to control a window in which a slave timer is enabled. the counter enable signal is generated by e ither the tim_cen control bit or the trigger input when configured in gated mode. when the counter enable signal is controlled by the trigger input there is a delay on trgo except if the master/slave mode is selected (see the tim_msm bit description in tmr x_smcr register). 010: update - uev is trigger output. this mode allows a master timer to be a prescaler for a slave timer. 011: compare pulse. the trigger output sends a positive pulse when the tim_cc1if flag is to be set (even if it was already high) as soon as a capture or a compare match occurs. 100: compare - oc1ref signal is trigger output. 101: compare - oc2ref signal is trigger output. 110: compare - oc3ref signal is trigger output. 111: compare - oc4ref signal is trigger output. 9 -33 120 - 035x - 000 rev. 1.2 final
EM351 / em357 timx_smcr tim1_smc r timer 1 slave mode control register address: 0x4000e008 reset: 0x0 tim2_smcr timer 2 slave mode control register address: 0x4000f008 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 tim_etp tim_ece tim_etps tim_etf 7 6 5 4 3 2 1 0 tim_msm tim_ts 0 tim_sms bitname bitfield access description tim_etp [15] rw external trigger polarity. this bit selects whether etr or the inverse of etr is used for trigger operations. 0: etr is non - inverted, active at a high level or rising edge. 1: etr is inverted, active at a low level or falling edge. tim_ece [14] rw external clock enable. this bit enables external clock mode 2. 0: external clock mode 2 disabled. 1: external clock mode 2 enabled. the counter is clocked by any active edge on the etrf signal. note 1: setting the tim_ece bit has the same effect as selecting external clock mode 1 with trgi connected to etrf (tim_sms=111 and tim_ts=111). note 2: it is possible to use this mod e simultaneously with the following slave modes: reset mode, gated mode and trigger mode. trgi must not be connected to etrf in this case (the tim_ts bits must not be 111). note 3: if external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input will be etrf. tim_etps [13:12] rw external trigger prescaler. external trigger signal etrp frequency must be at most 1/4 of ck frequency. a prescaler can be enabled to reduce etrp frequency. it is useful with fast external clocks. 00: etrp prescaler off. 01: divide etrp frequency by 2. 10: divide etrp frequency by 4. 11: divide etrp frequency by 8. 9 -34 120 - 035x - 000 rev. 1.2 final
EM351 / em357 bitname bitfield access description tim_etf [11:8] rw external trigger filter. this defines the frequency used to sample the etrp signal, fsampling, and the length of the digital filter applied to etrp. the digital filter is made of an event counter in which n events are needed to validate a transition on the output: 0000: fsampling=pclk, no filtering. 0001: fsampling=pclk, n=2. 0010: fsampling=pclk, n=4. 0011: fsam pling=pclk, n=8. 0100: fsampling=pclk/2, n=6. 0101: fsampling=pclk/2, n=8. 0110: fsampling=pclk/4, n=6. 0111: fsampling=pclk/4, n=8. 1000: fsampling=pclk/8, n=6. 1001: fsampling=pclk/8, n=8. 1010: fsampling=pclk/16, n=5. 1011: fsampling=pclk/16, n=6. 1100: fsampling=pclk/16, n=8. 1101: fsampling=pclk/32, n=5. 1110: fsampling=pclk/32, n=6. 1111: fsampling=pclk/32, n=8. note: pclk is 12 mhz when the em35x is using the 24 mhz crystal oscillator, and 6 mhz if using the 12 mhz rc oscillator. tim_msm [7] r w master/slave mode. 0: no action. 1: the effect of an event on the trigger input (trgi) is delayed to allow exact synchronization between the current timer and the slave (through trgo). it is useful for synchronizing timers on a single external event. ti m_ts [6:4] rw trigger selection. this bit field selects the trigger input used to synchronize the counter. 000 : internal trigger 0 (itr0). 100 : ti1 edge detector (ti1f_ed). 101 : filtered timer input 1 (ti1fp1). 110 : filtered timer input 2 (ti2fp2). 111 : external trigger input (etrf). note: these bits must be changed only when they are not used (when tim_sms=000) to avoid detecting spurious edges during the transition. tim_sms [2:0] rw slave mode selection. when external signals are selected the activ e edge of the trigger signal (trgi) is linked to the polarity selected on the external input. 000: slave mode disabled. if tim_cen = 1 then the prescaler is clocked directly by the internal clock. 001: encoder mode 1. counter counts up/down on ti1fp1 edge depending on ti2fp2 level. 010: encoder mode 2. counter counts up/down on ti2fp2 edge depending on ti1fp1 level. 011: encoder mode 3. counter counts up/down on both ti1fp1 and ti2fp2 edges depending on the level of the other input. 100: reset mode. rising edge of the selected trigger signal (trgi) >reinitializes the counter and generates an update of the registers. 101: gated mode. the counter clock is enabled when the trigger signal (trgi) is high. the counter stops (but is not reset) as soon as the trigge r becomes low. both starting and stopping the counter are controlled. 110: trigger mode. the counter starts at a rising edge of the trigger trgi (but it is not reset). only starting the counter is controlled. 111: external clock mode 1. rising edges of the selected trigger (trgi) clock the counter. note: gated mode must not be used if ti1f_ed is selected as the trigger input (tim_ts=100). ti1f_ed outputs 1 pulse for each transition on ti1f, whereas gated mode checks the level of the trigger signal. 9 -35 120 - 035x - 000 rev. 1.2 final
EM351 / em357 timx_ egr tim1_egr timer 1 event generation register address: 0x4000e014 reset: 0x0 tim2_egr timer 2 event generation register address: 0x4000f014 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 tim_tg 0 tim_cc4g tim_cc3g tim_cc2g tim_cc1g tim_ug bitname bitfield access description tim_tg [6] w trigger generation. 0: does nothing. 1: sets the tim_tif flag in the int_timxflag register. tim_cc4g [4] w capture/compare 4 generation. 0: does nothing. 1: if cc4 configured as output channel: the tim_cc4if flag is set. if cc4 configured as input channel: the tim_cc4if flag is set. the int_timmisscc4if flag is set if the tim_cc4if flag was already high. the cu rrent value of the counter is captured in tmrx_ccr4 register. tim_cc3g [3] w capture/compare 3 generation. 0: does nothing. 1: if cc3 configured as output channel: the tim_cc3if flag is set. if cc3 configured as input channel: the tim_cc3if flag is set. t he int_timmisscc3if flag is set if the tim_cc3if flag was already high. the current value of the counter is captured in tmrx_ccr3 register. tim_cc2g [2] w capture/compare 2 generation. 0: does nothing. 1: if cc2 configured as output channel: the tim_cc2if flag is set. if cc2 configured as input channel: the tim_cc2if flag is set. the int_timmisscc2if flag is set if the tim_cc2if flag was already high. the current value of the counter is captured in tmrx_ccr2 register. tim_cc1g [1] w capture/compare 1 gene ration. 0: does nothing. 1: if cc1 configured as output channel: the tim_cc1if flag is set. if cc1 configured as input channel: the tim_cc1if flag is set. the int_timmisscc1if flag is set if the tim_cc1if flag was already high. the current value of the counter is captured in tmrx_ccr1 register. tim_ug [0] w update generation. 0: does nothing. 1: re - initializes the counter and generates an update of the registers. this also clears the prescaler counter but the prescaler ratio is not affected. the counter is cleared if center - aligned mode is selected or if tim_dir=0 (up - counting), otherwise it takes the auto - reload value (tmr1_arr) if tim_dir=1 (down - counting). 9 -36 120 - 035x - 000 rev. 1.2 final
EM351 / em357 tim x _ccmr1 tim1_ccmr1 timer 1 capture/compare mode register 1 address: 0x4000e018 reset: 0x0 tim2_ccmr1 timer 2 capture/compare mode register 1 address: 0x4000f018 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 tim_oc2m tim_oc2be tim_oc2fe tim_cc2s tim_ic2f tim_ic2psc 7 6 5 4 3 2 1 0 0 tim_oc1m tim_oc1be tim_oc1fe tim_cc1s tim_ic1f tim_ic1psc timer channels can be programmed as inputs (capture mode) or outputs (compare mode). the direction of channel y is defined by tim_ccys in this register. the other bits in this register have different functions in input and in output modes. the tim_oc* fields only apply to a channel configured as an output (tim_ccys = 0), and the tim_ic* fields only apply to a channel configured as an input (tim_ccys > 0). bitname bitfield acces s description tim_oc2m [14:12] rw output compare 2 mode. (applies only if tim_cc2s = 0.) define the behavior of the output reference signal oc2ref from which oc2 derives. oc2ref is active high whereas oc2''s active level depends on the tim_cc2p bit. 000: frozen - the comparison between the output compare register timx_ccr2 and the counter timx_cnt has no effect on the outputs. 001: set oc2ref to active on match. the oc2ref signal is forced high when the counter timx_cnt matches the capture/compare register 2 (timx_ccr2) 010: set oc2ref to inactive on match. oc2ref signal is forced low when the counter timx_cnt matches the capture/compare register 2 (timx_ccr2). 011: toggle - oc2ref toggles when timx_cnt = timx_ccr2. 100: force oc2ref inactive. 101: force oc2ref active. 110: pwm mode 1 - in up - counting, oc2ref is active as long as timx_cnt < timx_ccr2, otherwise oc2ref is inactive. in down - counting, oc2ref is inactive if timx_cnt > timx_ccr2, otherwise oc2ref is active. 11 1: pwm mode 2 - in up - counting, oc2ref is inactive if timx_cnt < timx_ccr2, otherwise oc2ref is active. in down - counting, oc2ref is active if timx_cnt > timx_ccr2, otherwise it is inactive. note: in pwm mode 1 or 2, the oc2ref level changes only when the result of the comparison changes or when the output compare mode switches from ?frozen? mode to ?pwm? mode. tim_oc2be [11] rw output compare 2 buffer enable. (applies only if tim_cc2s = 0.) 0: buf fer register for timx_ccr2 is disabled. timx_ccr2 can be written at anytime, the new value is used by the shadow register immediately. 1: buffer register for timx_ccr2 is enabled. read/write operations access the buffer register. timx_ccr2 buffer value is loaded in the shadow register at each uev . note: the pwm mode can be used without enabling the buffer register only in one pulse mode (tim_opm bit set in the timx_cr2 register), otherwise the behavior is undefined. 9 -37 120 - 035x - 000 rev. 1.2 final
EM351 / em357 bitname bitfield acces s description tim_oc2fe [10] rw output compare 2 fast enable. (applies only if tim_cc2s = 0.) this bit speeds the effect of an event on the trigger in input on the oc2 output. 0: oc2 behaves normally depending on the counter and tim_ccr2 values even when the trigger is on. the minimum delay to activate oc2 w hen an edge occurs on the trigger input is 5 clock cycles. 1: an active edge on the trigger input acts like a compare match on the oc2 output. oc2 is set to the compare level independently from the result of the comparison. delay to sample the trigger inpu t and to activate oc2 output is reduced to 3 clock cycles. tim_oc2fe acts only if the channel is configured in pwm 1 or pwm 2 mode. tim_ic2f [15:12] rw input capture 1 filter. (applies only if tim_cc2s > 0.) this defines the frequency used to sample the t i2 input, fsampling, and the length of the digital filter applied to ti2. the digital filter requires n consecutive samples in the same state before being output. 0000: fsampling=pclk, no filtering. 0001: fsampling=pclk, n=2. 0010: fsampling=pclk, n=4. 001 1: fsampling=pclk, n=8. 0100: fsampling=pclk/2, n=6. 0101: fsampling=pclk/2, n=8. 0110: fsampling=pclk/4, n=6. 0111: fsampling=pclk/4, n=8. 1000: fsampling=pclk/8, n=6. 1001: fsampling=pclk/8, n=8. 1010: fsampling=pclk/16, n=5. 1011: fsampling=pclk/16, n=6. 1100: fsampling=pclk/16, n=8. 1101: fsampling=pclk/32, n=5. 1110: fsampling=pclk/32, n=6. 1111: fsampling=pclk/32, n=8. note: pclk is 12 mhz when using the 24 mhz crystal oscillator, and 6 mhz using the 12 mhz rc oscillator. tim_ic2psc [11:10] rw in put capture 1 prescaler. (applies only if tim_cc2s > 0.) 00: no prescaling, capture each time an edge is detected on the capture input. 01: capture once every 2 events. 10: capture once every 4 events. 11: capture once every 8 events. tim_cc2s [9:8] rw capture / compare 2 selection. this configures the channel as an output or an input. if an input, it selects the input source. 00: channel is an output. 01: channel is an input and is mapped to ti2. 10: channel is an input and is mapped to ti1. 11: channel is an input and is mapped to trgi. this mode requires an internal trigger input selected by the tim_ts bit in the timx_smcr register. note: tim_cc2s may be written only when the channel is off (tim_cc2e = 0 in the timx_ccer register). tim_oc1m [6:4] rw output compare 1 mode. (applies only if tim_cc1s = 0.) see tim_oc2m description above. tim_oc1be [3 rw output compare 1 buffer enable. (applies only if tim_cc1s = 0.) see tim_oc2be description above. tim_oc1fe [2] rw output compare 1 fast enable. (applies only if tim_cc1s = 0.) see tim_oc2fe description above. tim_ic1f [7:4] rw input capture 1 filter. (applies only if tim_cc1s > 0.) see tim_ic2f description above. tim_ic1psc [3:2] rw input capture 1 prescaler. (applies only if tim_cc1s > 0.) see tim_ic2psc description above. 9 -38 120 - 035x - 000 rev. 1.2 final
EM351 / em357 bitname bitfield acces s description tim_cc1s [1:0] rw capture / compare 1 selection. this configures the channel as an output or an input. if an input, it selects the input source. 00: channel is an output. 01: channel is an input and is mapped to ti1. 10: cha nnel is an input and is mapped to ti2. 11: channel is an input and is mapped to trgi. this requires an internal trigger input selected by the tim_ts bit in the tim_smcr register. note: tim_cc1s may be written only when the channel is off (tim_cc1e = 0 in the timx_ccer register). 9 -39 120 - 035x - 000 rev. 1.2 final
EM351 / em357 timx_ccmr2 tim1_ccmr2 timer 1 capture/compare mode register 2 address: 0x4000e01c reset: 0x0 tim2_ccmr2 timer 2 capture/compare mode register 2 address: 0x4000f01c reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 tim_oc4m tim_oc4be tim_oc4fe tim_cc4s tim_ic4f tim_ic4psc 7 6 5 4 3 2 1 0 0 tim_oc3m tim_oc3be tim_oc3fe tim_cc3s tim_ic3f tim_ic3psc timer channels can be programmed as inputs (capture mode) or outputs (compare mode). the direction of channel y is defined by tim_ccys in this register. the other bits in this register have different functions in input and in output modes. the tim_oc* fiel ds only apply to a channel configured as an output (tim_ccys = 0), and the tim_ic* fields only apply to a channel configured as an input (tim_ccys > 0). bitname bitfield access description tim_oc4m [14:12] rw output compare 4 mode. (applies only if tim_cc4s = 0.) define the behavior of the output reference signal oc4ref from which oc4 derives. oc4ref is active high whereas oc4 ? s active level depends on the tim_cc4p bit. 000: frozen - the comparison between the output compare register timx_ccr4 and the counter timx_cnt has no effect on the outputs. 001: set oc4ref to active on match. the oc4ref signal is forced high when the counter timx_cnt matches the capture/compare reg ister 4 (timx_ccr4) 010: set oc4ref to inactive on match. oc4ref signal is forced low when the counter timx_cnt matches the capture/compare register 4 (timx_ccr4). 011: toggle - oc4ref toggles when timx_cnt = timx_ccr4. 100: force oc4ref inactive. 101: for ce oc4ref active. 110: pwm mode 1 - in up - counting, oc4ref is active as long as timx_cnt < timx_ccr4, otherwise oc4ref is inactive. in down - counting, oc4ref is inactive if timx_cnt > timx_ccr4, otherwise oc4ref is active. 111: pwm mode 2 - in up - counting, oc4ref is inactive if timx_cnt < timx_ccr4, otherwise oc4ref is active. in down - counting, oc4ref is active if timx_cnt > timx_ccr4, otherwise it is inactive. note: in pwm mode 1 or 2, the oc4ref level changes only when the result of the comparison changes or when the output compare mode switches from ?frozen? mode to ?pwm? mode. tim_oc4be [11] rw output compare 4 buffer enable. (applies only if tim_cc4s = 0.) 0: buffer register for timx_ccr4 is disabled. timx_ccr4 can be written at anytime, the new value is used by the shadow register immediately. 1: buffer register for timx_ccr4 is enabled. read/write operations access the buffer register. timx_ccr4 buffer value is loaded in the shadow register at each uev . note: the pwm mode can be used without enabling the buffer register only in one pulse mode (tim_opm bit set in the timx_cr2 register), otherwise the behavior is undefined. 9 -40 120 - 035x - 000 rev. 1.2 final
EM351 / em357 bitname bitfield access description tim_oc4fe [10] rw output compare 4 fast enable. (applies only if tim_cc4s = 0.) this bit speeds the effect of an event on the trigger in input on the oc4 output. 0: oc4 behaves normally depending on the counter and tim_ccr4 values even when the trigger is on. the minimum delay to activate oc4 when an edge occurs on the trigger input is 5 clock cycles. 1: an active edge on the tri gger input acts like a compare match on the oc4 output. oc4 is set to the compare level independently from the result of the comparison. delay to sample the trigger input and to activate oc4 output is reduced to 3 clock cycles. tim_oc4fe acts only if the c hannel is configured in pwm 1 or pwm 2 mode. tim_ic4f [15:12] rw input capture 4 filter. (applies only if tim_cc4s > 0.) this defines the frequency used to sample the ti4 input, fsampling, and the length of the digital filter applied to ti4. the digital f ilter requires n consecutive samples in the same state before being output. 0000: fsampling=pclk, no filtering. 0001: fsampling=pclk, n=2. 0010: fsampling=pclk, n=4. 0011: fsampling=pclk, n=8. 0100: fsampling=pclk/2, n=6. 0101: fsampling=pclk/2, n=8. 0110: fsampling=pclk/4, n=6. 0111: fsampling=pclk/4, n=8. 1000: fsampling=pclk/8, n=6. 1001: fsampling=pclk/8, n=8. 1010: fsampling=pclk/16, n=5. 1011: fsampling=pclk/16, n=6. 1100: fsampling=pclk/16, n=8. 1101: fsampling=pclk/32, n=5. 1110: fsampling=pclk /32, n=6. 1111: fsampling=pclk/32, n=8. note: pclk is 12 mhz when using the 24 mhz crystal oscillator, and 6 mhz using the 12 mhz rc oscillator. tim_ic4psc [11:10] rw input capture 4 prescaler. (applies only if tim_cc4s > 0.) 00: no prescaling, capture e ach time an edge is detected on the capture input. 01: capture once every 2 events. 10: capture once every 4 events. 11: capture once every 8 events. tim_cc4s [9:8] rw capture / compare 4 selection. this configures the channel as an output or an input. if an input, it selects the input source. 00: channel is an output. 01: channel is an input and is mapped to ti4. 10: channel is an input and is mapped to ti3. 11: channel is an input and is mapped to trgi. this mode requires an internal trigger input select ed by the tim_ts bit in the timx_smcr register. note: tim_cc4s may be written only when the channel is off (tim_cc4e = 0 in the timx_ccer register). tim_oc3m [6:4] rw output compare 3 mode. (applies only if tim_cc3s = 0.) see tim_oc4m description above. tim_oc3be [3 rw output compare 3 buffer enable. (applies only if tim_cc3s = 0.) see tim_oc4be description above. tim_oc3fe [2] rw output compare 3 fast enable. (applies only if tim_cc3s = 0.) see tim_oc4fe description above. tim_ic3f [7:4] rw input capt ure 3 filter. (applies only if tim_cc3s > 0.) see tim_ic4f description above. tim_ic3psc [3:2] rw input capture 3 prescaler. (applies only if tim_cc3s > 0.) see tim_ic4psc description above. 9 -41 120 - 035x - 000 rev. 1.2 final
EM351 / em357 bitname bitfield access description tim_cc3s [1:0] rw capture / compare 3 selection. this configures the channel as an output or an input. if an input, it selects the input source. 00: channel is an output. 01: channel is an input and is mapped to ti3. 10: channel is an input and is mapped to ti4. 11: channel is an input and is mapped to trgi. this requires an internal trigger input selected by the tim_ts bit in the tim_smcr register. note: tim_cc3s may be written only when the channel is off (tim_cc3e = 0 in the timx_ccer register). 9 -42 120 - 035x - 000 rev. 1.2 final
EM351 / em357 timx_ccer tim1_ccer timer 1 capture/compare enable register address: 0x4000e020 reset: 0x0 tim2_ccer timer 2 capture/compare enable register address: 0x4000f020 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 tim_cc4p tim_cc4e 0 0 tim_cc3p tim_cc3e 7 6 5 4 3 2 1 0 0 0 tim_cc2p tim_cc2e 0 0 tim_cc1p tim_cc1e bitname bitfield access description tim_cc4p [13] rw capture/compare 4 output polarity. if cc4 is configured as an output channel: 0: oc4 is active high. 1: oc4 is active l o w. if cc4 configured as an input channel: 0: ic4 is not inverted. capture occurs on a rising edge of ic4. when used as an external trigger, ic4 is not inverted. 1 : ic4 is inverted. capture occurs on a falling edge of ic4. when used as an external trigge r, ic4 is inverted. tim_cc4e [12] rw capture/compare 4 output enable. if cc4 is configured as an output channel: 0: oc4 is disabled. 1: oc4 is enabled. if cc4 configured as an input channel: 0: capture is disabled. 1: capture is enabled. tim_cc3p [9] rw refer to the cc4p description above. tim_cc3e [8] rw refer to the cc4e description above. tim_cc2p [5] rw refer to the cc4p description above. tim_cc2e [4] rw refer to the cc43 description above. tim_cc1p [1] rw refer to the cc4p description above. tim_cc1e [0] rw refer to the cc4e description above. 9 -43 120 - 035x - 000 rev. 1.2 final
EM351 / em357 timx_cnt tim1_cnt timer 1 counter register address: 0x4000e024 reset: 0x0 tim2_cnt timer 2 counter register address: 0x4000f024 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 tim_cnt 7 6 5 4 3 2 1 0 tim_cnt bitname bitfield access description tim_cnt [15:0] rw counter value. 9 -44 120 - 035x - 000 rev. 1.2 final
EM351 / em357 timx_psc tim1_psc timer 1 prescaler register address: 0x4000e028 reset: 0x0 tim2_psc timer 2 prescaler register address: 0x4000f028 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 tim_psc bitname bitfield access description tim_psc [3:0] rw the prescaler divides the internal timer clock frequency. the counter clock frequency ck_cnt is equal to fck_psc / (2 ^ tim_psc). clock division factors can range from 1 through 32768. the division factor is loaded into the shadow prescaler regist er at each uev (including when the counter is cleared through tim_ug bit of tmr1_egr register or through the trigger controller when configured in reset mode). 9 -45 120 - 035x - 000 rev. 1.2 final
EM351 / em357 timx_arr tim1_arr timer 1 auto - reload register address: 0x4000e02c reset: 0xffff tim2_arr timer 2 auto - reload register address: 0x4000f02c reset: 0xffff 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 tim_arr 7 6 5 4 3 2 1 0 tim_arr bitname bitfield access description tim_arr [15:0] rw tim_arr is the value to be loaded in the shadow auto - reload register. the auto - reload register is buffered. writing or reading the auto - reload register accesses the buffer register. the content of the buffer register is transfered in the shadow r egister permanently or at each uev, depending on the auto - reload buffer enable bit (tim_arbe) in tmrx_cr1 register. the uev is sent when the counter reaches the overflow point (or underflow point when down - counting) and if the tim_udis bit equals 0 in the tmrx_cr1 register. it can also be generated by software. the counter is blocked while the auto - reload value is 0. 9 -46 120 - 035x - 000 rev. 1.2 final
EM351 / em357 timx_ccr1 tim1_ccr1 timer 1 capture/compare register 1 address: 0x4000e034 reset: 0x0 tim2_ccr1 timer 2 capture/compare register 1 address: 0x4000f034 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 tim_ccr 7 6 5 4 3 2 1 0 tim_ccr bitname bitfield access description tim_ccr [15:0] rw if the cc1 channel is configured as an output (tim_cc1s = 0): tim_ccr1 is the buffer value to be loaded in the actual capture/compare 1 register. it is loaded permanently if the preload feature is not selected in the tmr1_ccmr1 register (bit oc1pe). otherwise the buffer value is copied to the shadow capture/compare 1 register when an uev occurs. the active capture/compare register contains the value to be compared to the counter tmr1_cnt and signaled on the oc1 output. if the cc1 channel is configured as an input (tim_cc1s is not 0): ccr1 is the counter value transferred by the last input capture 1 event (ic1). 9 -47 120 - 035x - 000 rev. 1.2 final
EM351 / em357 timx_ccr2 tim1_ccr2 timer 1 capture/compare register 2 address: 0x4000e038 reset: 0x0 tim2_ccr2 timer 2 capture/compare register 2 address: 0x4000f038 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 tim_ccr 7 6 5 4 3 2 1 0 tim_ccr bitname bitfield access description tim_ccr [15:0] rw see description in the timx_ccr1 register. 9 -48 120 - 035x - 000 rev. 1.2 final
EM351 / em357 timx_ccr3 tim1_ccr3 timer 1 capture/compare register 3 address: 0x4000e03c reset: 0x0 tim2_ccr3 timer 2 capture/compare register 3 address: 0x4000f03c reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 tim_ccr 7 6 5 4 3 2 1 0 tim_ccr bitname bitfield access description tim_ccr [15:0] rw see description in the timx_ccr1 register. 9 -49 120 - 035x - 000 rev. 1.2 final
EM351 / em357 timx_ccr4 tim1_ccr4 timer 1 capture/compare register 4 address: 0x4000e040 reset: 0x0 tim2_ccr4 timer 2 capture/compare register 4 address: 0x4000f040 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 tim_ccr 7 6 5 4 3 2 1 0 tim_ccr bitname bitfield access description tim_ccr [15:0] rw see description in the timx_ccr1 register. 9 -50 120 - 035x - 000 rev. 1.2 final
EM351 / em357 tim1_or timer 1 option register address: 0x4000e050 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 tim_orrsvd tim_clkmsken tim _extrigsel bitname bitfield access description tim_orrsvd [3] rw reserved: this bit must always be set to 0. tim_clkmsken [2] rw enables tim1msk when tim1clk is selected as the external trigger: 0 = tim1msk not used, 1 = tim1clk is anded with the tim1msk input. tim _extrigsel [1:0] rw selects the external trigger used in external clock mode 2: 0 = pclk, 1 = calibrated 1 khz clock, 2 = 32 khz reference clock (if available), 3 = tim1clk pin. 9 -51 120 - 035x - 000 rev. 1.2 final
EM351 / em357 tim2_or timer 2 option register address: 0x 4000f050 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 tim_remapc4 tim_remapc3 tim_remapc2 tim_remapc1 tim_orrsvd tim_clkmsken tim _extrigsel bitname bitfield access description tim_remapc4 [7] rw selects the gpio used for tim2c4: 0 = pa2, 1 = pb4. tim_remapc3 [6] rw selects the gpio used for tim2c3: 0 = pa1, 1 = pb3. tim_remapc2 [5] rw selects the gpio used for tim2c2: 0 = pa3, 1 = pb2. tim_remapc1 [4] rw selects the gpio used for tim2c1: 0 = pa0, 1 = pb1. tim_orrsvd [3] rw reserved: this bit must always be set to 0. tim_clkmsken [2] rw enables tim2msk when tim2clk is selected as the external trigger: 0 = tim2msk not used, 1 = tim2clk is anded with the tim2msk input. tim _extrigsel [1:0] rw selects the external trigger used in external clock mode 2: 0 = pclk, 1 = calibrated 1 khz clock, 2 = 32 khz reference clock (if available), 3 = tim2clk pin. 9 -52 120 - 035x - 000 rev. 1.2 final
EM351 / em357 int_timxcfg int_tim1cfg timer 1 interrupt configuration register address: 0x4000a840 reset: 0x0 int_tim2cfg timer 2 interrupt configuration register address: 0x4000a844 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 int_timtif 0 int_timcc4if int_timcc3if int_timcc2if int_timcc1if int_timuif bitname bitfield access description int_timtif [6] rw trigger interrupt enable. int_timcc4if [4] rw capture or compare 4 interrupt enable. int_timcc3if [3] rw capture or compare 3 interrupt enable. int_timcc2if [2] rw capture or compare 2 interrupt enable. int_timcc1if [1] rw capture or compare 1 interrupt enable. int_timuif [0] rw update interrupt enable. 9 -53 120 - 035x - 000 rev. 1.2 final
EM351 / em357 int_timx flag int_tim1flag timer 1 interrupt flag register address: 0x4000a800 reset: 0x0 int_tim2flag timer 2 interrupt flag register address: 0x4000a804 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 int_timrsvd 0 7 6 5 4 3 2 1 0 0 int_timtif 0 int_timcc4if int_timcc3if int_timcc2if int_timcc1if int_timuif bitname bitfield access description int_timrsvd [12:9] r may change during normal operation. int_timtif [6] rw trigger interrupt. int_timcc4if [4] rw capture or compare 4 interrupt pending. int_timcc3if [3] rw capture or compare 3 interrupt pending. int_timcc2if [2] rw capture or compare 2 interrupt pending. int_timcc1if [1] rw capture or compare 1 interrupt pending. int_timuif [0] rw update interrupt pending. 9 -54 120 - 035x - 000 rev. 1.2 final
EM351 / em357 int_timxmiss int_tim1miss timer 1 missed interrupt register address: 0x4000a818 reset: 0x0 int_tim2miss timer 2 missed interrupts register address: 0x4000a81c reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 int_timmisscc4if int_timmisscc3if int_timmisscc2if int_timmisscc1if 0 7 6 5 4 3 2 1 0 0 int_timmissrsvd bitname bitfield access description int_timmisscc4if [12] rw capture or compare 4 interrupt missed. int_timmisscc3if [11] rw capture or compare 3 interrupt missed. int_timmisscc2if [10] rw capture or compare 2 interrupt missed. int_timmisscc1if [9] rw capture or compare 1 interrupt missed. int_timmissrsvd [6:0] r may change during normal operation. 9 -55 120 - 035x - 000 rev. 1.2 final
EM351 / em357 10 adc ( analog to digital converter ) the em35x adc is a first - order sigma - delta converter with the following features: ? r esolution of up to 14 bits ? s ample times as fast as 5.33 s (188 khz) ? d ifferential and single - ended conversions from six external and four internal sources ? one voltage range (differential): - vref to +vref ? c hoice of internal or external vref ? internal vref may be output to pb0 or external vref may be derived from pb0 ? d ig ital offset and gain correction ? d edicated dma channel with one - shot and continuous operating modes figure 10 - 1 shows the basic adc structure . figure 10 - 1 . adc block d iagram delta sigma adc decimator sample clock 1 mhz 6 mhz ` vref vref / 2 gnd vdd _ padsa / 2 gpio ` ` p input mux vref vref / 2 gnd vdd _ padsa / 2 gpio n input mux adc _ data register or dma offset and gain correction while the adc module supports both single - ended and differential inputs, the adc input stage always operates in differential mode . single - ended conversions are performed by connecting one of the differential inputs to vref/2 while fully differential operation uses two external inputs . note: the regulator input v oltage, vdd_pads, cannot be measured using the adc, but it can be measured through ember software. 10.1 set u p and configuration to use the adc follow this procedure, described in more detail in the next sections : ? configure a ny gpio pins to be used by the adc in analog mode. ? configure the voltage reference (internal or external) . ? set the offset and gain values. ? if using dma, r eset the adc dma, define the dma buffer, and start the dma in the proper transfer mode. 10- 1 120 - 035x - 000 rev. 1.2 final
EM351 / em357 ? if interrupts will be used, configure the top - level and second - level adc interrupt bits . ? write the adc configuration register to define the inputs , sample time , and start the conversions . 10.1.1 gpio usage a gpio pin used by the adc as an input or voltage r eference must be configured in analog mode by writing 0 to its 4 - bit field in the proper gpio_p x cfgh/l register. note that a gpio pin in analog mode cannot be used for any digital functions, and gpio_pxin always read s it as 1. only certain pins can be configured in analog mode . t hese are listed in table 10 - 1 . table 10- 1 . adc gpio pin usage analog signal gpio configuration control adc0 input pb5 gpio_pbcfgh[7:4] adc1 input pb6 gpio_pbcfgh[11:8] adc2 input pb7 gpio_pbcfgh[15:12] adc3 input pc1 gpio_pccfg l [7:4] adc4 input pa4 gpio_pacfgh[3:0] adc5 input pa5 gpio_pacfgh[7:4] vref input or output pb0 gpio_pbcfg l [3:0] see chapter 7, gpio for more information about how to configure gpio. 10.1.2 voltage reference the adc voltage reference ( vref ) , may be internally generated or externally sourced from pb0 . if internally generated, it may optionally be output on pb0 . to output the internal vref on p b 0 , the adc must be enabled (adc_enable bit set in the adc_cfg register) and pb 0 must be configured in analog mode. to use an external reference, the ember software must be called after reset and after waking from deep sleep. pb0 must also be configured in analog mode using gpio_pbcfgh[3:0]. see the ember software documentation for more information on using an external reference. 10.1.3 offset/gain correction when a conversion is complete, the 16 - bit converted data is processed in several steps by offset/gain corr ection hardware : 1. the initial signed adc conversion result is added to the 16 - bit signed ( two?s complement ) value of the adc offset regis ter ( adc_offset ) . 2. the offset - corrected data is multiplied by the 16 - bit adc gain register, adc_g ain, to produce a 16 - bit signed result. if the product is greater than 0x7fff (32767) , or less tha n 0x8000 ( - 32768) , it is limited to that value and the int_adcsat bit is set in the int_adcflag register. 3. the offset/gain corrected value is divided by two to produce the final resul t. adc_gain is a n unsigned scaled 16 - bit value: adc_gain[15] i s the integer part of the gain factor and adc_gain[14:0] is the fractional part. as a result, adc_gain values can represent gain factors from 0 through (2 ? 2 - 15 ). although adc_gain can represe nt a much greater range, its purpose is to correct small gain error, and in practice is loaded with values within a range of about 0.95 to 1.05. 10- 2 120 - 035x - 000 rev. 1.2 final
EM351 / em357 reset initializes the offset to zero (adc_offset = 0) and gain factor to one (adc_gain = 0x8000). 10.1.4 dma the adc dma channel writes converted data , which incorporates the offset/gain correction , in to a dma buffer in ram. the adc dma buffer is defined by two registers: ? adc_dmabeg is the start address of the buffer and must be even . ? adc_dmasize specifies the size of the buffer in 16 - bit samples , or half it s length in bytes. to prepare the dma channel for operation, reset it by writing the adc_dmarst bit in the adc_dmacfg regis ter, t he n start the dma in either linear or auto wrap mode by setting the adc_dmaloa d bit in the adc_dmacfg register . the adc_dmaautowrap bit in the adc_dmacfg register select s the dma mode: 0 for linear mode, 1 for auto wrap mode. ? in linear mode the dma writes to the buffer until the number of samples given by a d c_ dmasize has been output . t h e dma then stops and sets the int_adc uld full bit in the int _adcflag register. if another adc conversion completes before the dma is reset or the adc is disabled, the int_adcovf bit in the int_adcflag register is set. ? in auto wrap mode the dma writes to the buffer until it reaches the end , then resets its pointer to the start of the buffer and continu es writing samples . the dma transfer s continue until the adc is disabled or the dma is reset. when the dma fills the lower and upper halves of the buffer, it sets the int_adculdhalf and int_adculdfull bits, respectively, in the int_adcflag register. the current location to which the dma is writing can also be determined by reading the adc_dmacur register. 10.1.5 adc configuration register the adc configuration regi ster (adc_cfg) sets up m ost of the adc operating parameters . 10.1.5.1 input t he analog input of the adc can be chosen from various sources. the analog input is configured with the adc_muxp and adc_muxn bits with in the adc_cfg register. table 10 - 2 shows the possible input selections. 10- 3 120 - 035x - 000 rev. 1.2 final
EM351 / em357 table 10- 2 . adc i nputs adc_muxn 1 analog source at adc gpio pin purpose 0 adc0 pb5 1 adc1 pb6 2 adc2 pb7 3 adc3 pc 1 4 adc4 pa4 5 adc5 pa5 6 no connection 7 no connection 8 gnd internal connection calibration 9 vref/2 internal connection calibration 10 vref internal connection calibration 11 vdd_pads a /2 internal connection supply monitoring and calibration 12 no connection 13 no connection 14 no connection 15 no connection 1 denotes bits adc_muxp or adc_muxn in register adc_cfg. table 10 - 3 shows the typical configurations of adc inputs. table 10- 3 . typical adc i nput c onfigurations adc p input adc n input adc_muxp adc_muxn purpose adc0 vref/2 0 9 single - ended adc1 vref/2 1 9 single - ended adc2 vref/2 2 9 single - ended adc3 vref/2 3 9 single - ended adc4 vref/2 4 9 single - ended adc5 vref/2 5 9 single - ended adc1 adc0 1 0 differential adc3 adc2 3 2 differential adc5 adc4 5 4 differential gnd vref/2 8 9 calibration vref vref/2 10 9 calibration vdd_padsa/2 vref/2 11 9 calibration 10- 4 120 - 035x - 000 rev. 1.2 final
EM351 / em357 10.1.5.2 input range t he single - ended input range is fixed as 0 v to vref and the differential input range is fixed as - vref to +vref. 10.1.5.3 sample time a dc sample time is programmed by selecting the sampling clock and the c lock s per sample. ? the sam pling clock may be either 1 mhz or 6 mhz. if the adc_1mhzclk bit in the adc_ cfg reg ister is clear, the 6 mhz cl ock is used; if it is set, the 1 mhz clock is selected. the 6 mhz sample clock offers faster conversion times but the adc resolution is lower than that achieved with the 1 mhz clock. ? the number of clocks per sample is determined by the adc_period bit s in the adc_cfg re gister . adc_period values select from 32 to 4096 sampling clocks in powers of two. longer sample times produ ce more significant bits . regardless of the sample time, c onverted samples are always 16 - bits in size with the significant bits left - aligned within the value. table 10 - 4 shows the options for adc sample time s and the significant bits in the conversion results . table 10- 4 . adc sample times adc_period sample clocks sample time ( s ) sample f r eq uency ( k hz) significant bits 1 mhz clock 6 mhz clock 1 mhz clock 6 mhz clock 0 32 32 5.33 31.3 188 7 1 64 64 10. 7 15.6 93.8 8 2 128 128 21. 3 7 . 81 46.9 9 3 256 256 42. 7 3 . 9 1 23.4 10 4 512 512 85.3 1 . 95 11.7 11 5 1024 1024 170 0. 97 7 5 . 8 6 12 6 2048 2048 341 0. 488 2 . 93 13 7 4096 4096 682 0. 24 4 1 . 4 7 14 note: adc sample timing is the same whether the em35x is using the 24 mhz crystal oscillator or the 12 mhz high - speed rc oscillator. this facilitates using the adc soon after the cpu wakes from deep sleep, before switching to the crystal oscillator. 10.2 interrupts the adc has its own top - level interrupt in the nvic . the adc interrupt is enabled by writing the int_adc bit to the int_cfgset register, and cleared by wr iting the int_adc bit to the int_cfgclr register. chapter 11, interrupt system, describes the interrupt system in detail. five kinds of adc events can generate an adc interrupt , and e ach has a bit flag in the int_adcflag register to identify the reason(s) for the interrupt : ? int_adcovf ? an adc conversion result was ready but the dma was disabled (dma buffer overflow) . ? int_adcsat ? the gain correction multiplication exceeded the limits for a signed 16 - bit number (gain saturation) . 10- 5 120 - 035x - 000 rev. 1.2 final
EM351 / em357 ? int_adculdful l ? the dma wrote to the last location in the buffer ( dma buffer full ) . ? int_adculdhalf ? the dma wrote to the last location of the first half of the dma buffer ( dma buffer half full ) . ? int_adcdata ? there is data ready in the adc_data register. bits in int_adcflag register may be cleared by writing a 1 to th eir position. writing 0 to any bit in the int_adcflag register is ineffectual. the int_adccfg register controls whether or not int_adcflag register bits actually propagate the adc interrupt to the nvi c . o nly the events whose bits are 1 in the int_adccfg register can do so. for non - interrupt (polled) adc operation set the int_adccfg register to zero, and read the bit flags in the int_adcflag register to determine the adc status. note: when making changes to t he adc configuration it is best to disable the dma beforehand. if this isn?t done it can be difficult to determine at which point the sample d data in the dma buffer switch ed from the old configuration to the new configuration. however, since the adc will b e left running, if it complete s a conversion after the dma is disabled , the int_adcovf flag will be set. to prevent these unwanted dma buffer overflow indications, clear the int_adcovf flag immediately after enabling the dma, preferably with interrupts off . disabling the adc in addition to the dma is often undesirable because of the additional analog startup time when it is re - enabled. 10.3 operation s etting the adc_ en bit in the adc_cfg register enables the adc . o nce the adc is enabled, it perform s conversions continuously until it is disabled. if the ad c had previously been disabled, a 21 s analog startup delay is automatically imposed before the adc starts conversions. the delay timing is performed in hardware and is simply added to the time until the first conversion result is output. when the adc is first enabled, and/ or if any change is made to adc_cfg after it is enabled , the time until a result is output is double the normal sample time. this is because the adc?s internal design requires it to discard th e first conversion after startup or a c onfiguration change . t his is done automatically and is hidden from software . switching the system clock between oschf and osc24m also causes the adc to go through this startup cycle. if the adc was newly enabled, the analog delay time is added to the doubled sample time. if the dma is running when the adc_cfg register is modified, the dma does not stop , so the dma buffer may contain conversion results from both the old and new configurations. the followin g procedure illustrates a simple polled method of using the adc without dma. this assumes that any gpios and the voltage reference have already been configured. 1. disable all adc interrupts: write 0 to the int_adccfg register . 2. write the desired offset and gain correction values to the adc_offset and adc_gain registers. 3. write the desired conversion configuration, with the adc_en bit set, to adc_cfg register . 4. clear the adc data flag: write the int_adc data bit to int_adcflag register. 5 . wait until the int_adc data bit is set in int_adcflag register , then read the result , as a 16- bit signed variable , from the adc_data register . the following procedure illus trates a simple polled method of using the adc with dma . after completing the procedure, t he latest conversion result s are available in the location written to by the dma. this assumes that any gpios and the voltage reference have already been configured. 1. allocate a 16 - bit signed variable, for example analogdata, to receive the adc output. (make sure that analogdata is half - word aligned ? that is, at an even address.) 2. disable all adc interrupts: write 0 to the int_adccfg register . 10- 6 120 - 035x - 000 rev. 1.2 final
EM351 / em357 3. set up the dma to output conversion results to the variable, analogdata. reset the dma: set the adc_dmarst bit in adc_dmacfg register . define a one sample buffer: write analogdata?s address to the adc_dmabeg register and set the adc_dmasize register to 1. 4. write the desired offset and gain correction values to the adc_offset and adc_gain registers. 5. start the adc and the dma. write the desired conversion configuration, with the adc_en bit set, to the adc_cfg register . clear the adc buffer full flag: write the int_adculdfull bit to the int_adcflag register . start the dma in auto wrap mode: set the adc_dmaaut owrap and adc_dmaload bits in the adc_dmacfg register . 6. wait until the int_adculdfull bit is set in the int_adcflag register , then read the result from analogdata. to convert multiple inputs using this approach, repea t steps 4 through 6 , loading the des ired input configuration s to the adc_cfg register in step 5 . if the inputs can use the same offset/gain correction, just repeat step s 5 and 6. 10.4 calibration sampling of internal connections gnd , vref/2, and vref allow for offset and gain calibration of the adc in applications where absolute accuracy is important. offset error is calculated from the minimum input and g ain error is calculated from the full scale input range. correction using vref is recommended because vref is calibrated by the ember software against vdd_padsa. the vdd_padsa regulator is factory - trimmed to 1.80 v 20 mv . if better absolute accuracy is required , t he adc can be configured to use a n external reference . t he adc calibr ates as a single - ended measurement. differential signals require c orrection of both their inputs. the following steps outline the calibration procedure ? calibrate vref against vdd_padsa . ? determine the adc gain by sampling independently vref and gnd . gain i s calculated from the slope of these two measurements . ? apply gain correction . ? determine the adc offset by sampling gnd . ? apply offset correction . table 10 - 5 show s the equations used to calculate the gain and offset correction values . table 10- 5 . adc gain and offset correction equations calibration co rrection value gain ) ( 16384 32768 gnd vref n n ? ) 57344 ( 2 gnd n ? equation notes ? the adc output is two?s complement. all n are therefore 16 - bit two?s complement numbers . ? offset is a 16 - bit two ?s complement number . ? gain is a 16 - bit number representing a gain of 0 to 65535/32768 in 1/32768 steps. the default value is 32768 , corresponding to a gain of 1. ? n gnd is a sampling of ground. due to the adc's internal design, v gnd does not yield the minimum 16 bit two?s complement value 32768 as the conversion result . instead, vgnd yields a value close to 57344 when 10- 7 120 - 035x - 000 rev. 1.2 final
EM351 / em357 the input buffer is not selected. vgnd cannot be measured when the input buffer is enabled because it is outside th e buffer?s input range. ? n vref is a sa mpling of vref. due to the adc's internal design, vref does not yield the maximum positive 16- bit two?s complement 32767 as the conversion result . instead, vref yields a value close to 8192 . ? n vref/2 is a sampling of vref/2. vref/2 yields a value close to 0 . ? offset correction is affected by the gain correction value. offset correction is calculated after gain correction has been applied. 10.5 adc key parameters table 10 - 6 describes the key adc parameter s measured at 25 c and vdd_pads at 3.0 v , for a sampling clock of 1 mhz . the single - ended measurements were done at f input = 7.7% f nyquist ; 0 dbfs level (where full - scale is a 1.2 v p - p swing). the differential measurements were done at f input = 7.7% f nyquist ; - 6 dbfs level (where full - scale is a 2.4 v p - p swing) and a common mode voltage of 0.6 v. table 10- 6 . adc module key parameters for 1 mhz sampling parameter performance adc_period 0 1 2 3 4 5 6 7 conversion time ( s) 32 64 128 256 512 1024 2048 4096 nyquist freq (khz) 15.6k 7.81k 3.91k 1.95k 977 488 244 122 3 db cut - off (khz) 9.43k 4.71k 2.36k 1.18k 589 295 147 73.7 inl (codes peak) 0.083 0.092 0.163 0.306 0.624 1.229 2.451 4.926 inl (codes rms) 0.047 0.051 0.093 0.176 0.362 0.719 1.435 2.848 dnl (codes peak) 0.028 0.035 0.038 0.044 0.074 0.113 0.184 0.333 dnl (codes rms) 0.008 0.009 0.011 0.014 0.019 0.029 0.048 0.079 enob (from single - cycle test) 5.6 7.0 8.6 10.1 11.5 12.6 13.0 13.2 10- 8 120 - 035x - 000 rev. 1.2 final
EM351 / em357 parameter performance snr (db) single - ended differential 35 35 44 44 53 53 62 62 70 71 75 77 77 79 77 80 sinad (db) single - ended differential 35 35 44 44 53 53 61 62 67 70 69 75 70 76 70 76 sdfr (db) single - ended differential 59 60 68 69 72 77 72 80 72 81 72 81 72 81 73 81 thd (db) single - ended differential - 45 - 45 - 54 - 54 - 62 - 63 - 67 - 71 - 69 - 75 - 69 - 76 - 69 - 76 - 69 - 76 enob (from snr) single - ended differential 5.6 5.6 7.1 7.1 8.6 8.6 10.0 10.1 11.3 11.4 12.2 12.5 12.4 12.9 12.5 12.9 enob (from sinad) single - ended differential 5.5 5.6 7.0 7.0 8.5 8.5 9.9 10.0 10.9 11.3 11.2 12.1 11.3 12.3 11.3 12.4 equivalent adc bits 7 [15:9] 8 [15:8] 9 [15:7] 10 [15:6] 11 [15:5] 12 [15:4] 13 [15:3] 14 [15:2] note: inl and dnl are referenced to a lsb of the equivalent adc bits shown in the last row of table 10- 6 . enob (effective number of bits) can be calculated from either snr (signal to non - harmonic noise ratio) or sinad (signal - to - noise and distortion ratio). table 10 - 7 describes the key adc parameter s measured at 25 c and vdd_pads at 3.0 v, for a sampling rate of 6 mhz. the single - ended measurements were done at f input = 7.7% f nyquist ; 0 dbfs level (where full - scale is a 1.2 v p - p swing). the differential measurements were done at f input = 7.7% f nyquist ; - 6 dbfs level (where full - scale is a 2.4 v p - p swing) and a common mode voltage of 0.6 v . table 10- 7 . adc module key parameters for 6 mhz sampling parameter performance adc_ period 0 1 2 3 4 5 6 7 conversion time ( s) 5.33 10.7 21.3 42.7 85.3 171 341 683 nyquist freq (khz) 93.8k 46.9k 23.4k 11.7k 5.86k 2.93k 1.47k 732 3 db cut - off (khz) 56.6k 28.3k 14.1k 7.07k 3.54k 1.77k 884 442 inl (codes peak) 0.084 0.084 0.15 0.274 0.518 1.057 2.106 4.174 inl (codes rms) 0.046 0.044 0.076 0.147 0.292 0.58 1.14 2.352 dnl (codes peak) 0.026 0.023 0.044 0.052 0.096 0.119 0.196 0.371 10- 9 120 - 035x - 000 rev. 1.2 final
EM351 / em357 parameter performance dnl (codes rms) 0.007 0.009 0.013 0.015 0.024 0.03 0.05 0.082 enob (from single - cycle test) 5.6 7.0 8.5 10.0 11.4 12.6 13.1 13.2 snr (db) single - ended differential 35 35 44 44 53 53 62 62 70 71 75 77 76 79 7 7 80 sinad (db) single - ended differential 35 35 44 44 53 53 62 62 68 70 71 75 71 77 71 77 sdfr (db) single - ended differential 60 60 68 69 75 77 75 80 75 80 75 80 75 80 75 80 thd (db) single - ended differential - 45 - 45 - 54 - 54 - 63 - 63 - 68 - 71 - 70 - 76 - 7 0 - 77 - 7 0 - 78 - 7 0 - 78 enob (from snr) single - ended differential 5.6 5.6 7.1 7.1 8.6 8.6 10.0 10.1 11.4 11.5 12.1 12.5 12.4 12.9 12.5 13.0 enob (from sinad) single - ended differential 5.5 5.6 7 .0 7 .1 8.5 8.6 9.9 10.1 11.0 11.4 11.4 12.4 11.5 12.8 11.5 13.0 equivalent adc bits 7 [15:9] 8 [15:8] 9 [15:7] 10 [15:6] 11 [15:5] 12 [15:4] 13 [15:3] 14 [15:2] note: inl and dnl are referenced to a lsb of the equivalent adc bits shown in the last row of table 10- 7 . enob (effective number of bits) can be calculated from either snr (signal to non - harmonic noise ratio) or sinad (signal - to - noise and distortion ratio). table 10 - 8 describes the key adc parameters measured at 25 c and vdd_pads at 3.0 v, for a sampling clock of 6 mhz. the single - ended measurements were done at f input = 7.7% f nyquist ; level = 1.2 v p - p swing centered on 1.5 v. the differential measurements were done at f input = 7.7% f nyquist , level = 1.2 v p - p swing and a common mode voltage of 1.5 v. table 10- 8 . adc module key parameters for input buffer en abled and 6 mhz sampling parameter performance adc_period 0 1 2 3 4 5 6 7 conversion time (s) 32 64 128 256 512 1024 2048 4096 nyquist freq (khz) 93.8k 46.9k 23.4k 11.7k 5.86k 2.93k 1.47k 732 3 db cut - off (khz) 56.6k 28.3k 14.1k 7.07k 3.54k 1.77k 884 442 10- 10 120 - 035x - 000 rev. 1.2 final
EM351 / em357 parameter performance inl (codes peak) 0.055 0.032 0.038 0.07 0.123 0.261 0.522 1.028 inl (codes rms) 0.028 0.017 0.02 0.04 0.077 0.167 0.326 0.65 dnl (codes peak) 0.028 0.017 0.02 0.04 0.077 0.167 0.326 0.65 dnl (codes rms) 0.01 0.006 0.006 0.007 0.008 0.013 0.023 0.038 enob (from single - cycle test) 3.6 5.0 6.6 8.1 9.5 10.7 11.3 11.6 snr (db) single - ended differential 23 23 32 32 41 41 50 50 59 59 65 66 67 69 68 71 sinad (db) single - ended differential 23 23 32 32 41 41 50 50 58 59 64 66 66 69 66 71 sdfr (db) single - ended differential 48 48 56 57 65 65 72 74 7 2 82 72 88 73 88 73 88 thd (db) single - ended differential - 33 - 33 - 42 - 42 - 51 - 51 - 59 - 60 - 66 - 69 - 68 - 76 - 68 - 80 - 68 - 82 enob (from snr) single - ended differential 3.6 3.6 5.1 5.1 6.6 6.6 8.1 8.1 9.5 9.5 10.5 10.7 10.9 11.3 11 11.5 enob (from sinad) single - ended differential 3.6 3.6 5.0 5.1 6.5 6.6 8 .0 8 .0 9.4 9.5 10.3 10.6 10.7 11.3 10.7 11.4 equivalent adc bits 7 [15:9] 8 [15:8] 9 [15:7] 10 [15:6] 11 [15:5] 12 [15:4] 13 [15:3] 14 [15:2] inl and dnl are referenced to a lsb of the equivalent adc bits shown in the last row of table 10- 6 . enob (effective number of bits) can be calculated from either snr (signal to non - harmonic noise ratio) or sinad (signal - to - noise and distortion ratio). table 10 - 9 lists other specifications for the adc not covered in table 10 - 6 and table 10- 7 . table 10- 9 . adc specifications parameter min. typ. max. units vref 1.17 1.2 1.23 v vref output current 1 ma 10- 11 120 - 035x - 000 rev. 1.2 final
EM351 / em357 parameter min. typ. max. units vref load capacitance 10 nf external vref voltage range 1.1 1.2 1.3 v external vref input impedance 1 m minimum input voltage 0 v maximum input voltage vref v single - ended signal range 0 vref v differential signal range - vref +vref v common mode range 0 vref v input referred adc offset - 10 10 mv input impedance 1 mhz sample clock 6 mhz sample clock not sampling 1 0.5 10 m note: the signal - ended adc measurements are limited in their range and only guaranteed for accuracy within the limits shown in this table . t he adc's internal design allows for measurements outside of this range ( 200 mv) , but the accuracy of such measurements is not guaranteed . the maximum input voltage is of more interest to the differential sampling where a differential measurement might be small, but a common mode can push the actual input voltage o n one of the signals towards the upper voltage limit. 10- 12 120 - 035x - 000 rev. 1.2 final
EM351 / em357 10.6 registers adc_ data adc data register address: 0x4000d000 reset: 0x00000000 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 adc_data_field 7 6 5 4 3 2 1 0 adc_data_field bitname bitfield access description adc_data_field [15:0] r adc conversion result. the result is a signed 2?s complement value. the significant bits of the value begin at bit 15 regardless of the sample period used. 10- 13 120 - 035x - 000 rev. 1.2 final
EM351 / em357 adc_ cfg adc configuration register address: 0x4000d004 reset: 0x00001800 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 adc_period adc_ cfg rsvd 2 adc_muxp 7 6 5 4 3 2 1 0 adc_muxp adc_muxn adc_1mhzclk adc_cfgrsvd adc_enable bitname bitfield access description adc_period [15:13] rw adc sample time in clocks and the equivalent significant bits in the conversion. 0: 32 clocks ( 7 bits). 1: 64 clocks ( 8 bits). 2: 128 clocks ( 9 bits). 3: 256 clocks ( 10 bits). 4: 512 clocks ( 11 bits). 5: 1024 clocks (1 2 bits). 6: 2048 clocks (1 3 bits). 7: 4096 clocks (1 4 bits). adc_ cfg rsvd 2 [12 :11 ] rw reserved: these bits must be set to 0. adc_muxp [10:7] rw input selection for the p channel. 0x0: pb5 pin. 0x1: pb6 pin. 0x2: pb7 pin. 0x3: pc1 pin. 0x4: pa4 pin. 0x5: pa5 pin. 0x8: gnd (0v) (not for high voltage range). 0x9: vref/2 (0.6v). 0xa: vref (1.2v). 0xb: vdd_padsa /2 (0.9v) (not for high voltage range). 0x6, 0x7, 0xc - 0xf: reserved. adc_muxn [6:3] rw input selection for the n channel. refer to adc_muxp above for choices. adc_1mhzclk [2] rw select adc clock: 0 = 6 mhz, 1 = 1 mhz. adc_cfgrsvd [1] rw reserved: this bit must always be set to 0. adc_enable [0] rw enable the adc: write 1 to enable continuous conversions, write 0 to stop. when the adc is started the first conversion takes twice the usual number of clocks plus 21 microseconds. if anything in this register is modified while the adc is running, the next conversion takes twice the usual number of clocks. 10- 14 120 - 035x - 000 rev. 1.2 final
EM351 / em357 adc_offset adc offset register address: 0x4000d008 reset: 0x0000 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 adc_offset_field 7 6 5 4 3 2 1 0 adc_offset_field bitname bitfield access description adc_offset_field [15:0] rw 16 - bit signed offset added to the basic adc conversion result before gain correction is applied. 10- 15 120 - 035x - 000 rev. 1.2 final
EM351 / em357 adc_gain adc gain register address: 0x4000d00c reset: 0x8000 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 adc_gain_field 7 6 5 4 3 2 1 0 adc_gain_field bitname bitfield access description adc_gain_field [15:0] rw gain factor that is multiplied by the offset - corrected adc result to produce the output value. the gain is a 16 - bit unsigned scaled integer value with a binary decimal point between bits 15 and 14. it can represent values from 0 to (almost) 2. the reset value i s a gain factor of 1. 10- 16 120 - 035x - 000 rev. 1.2 final
EM351 / em357 adc_dmacfg adc dma configuration register address: 0x4000d010 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 adc_dmarst 0 0 adc_dmaautowra p adc_dmaload bitname bitfield access description adc_dmarst [4] w write 1 to reset the adc dma. this bit auto - clears. adc_dmaautowrap [1] rw selects dma mode. 0: linear mode, the dma stops when the buffer is full. 1: auto - wrap mode, the dma output wraps back to the start when the buffer is full. adc_dmaload [0] rw loads the dma buffer. write 1 to start dma (writing 0 has no effect). cleared when dma starts or is reset. 10- 17 120 - 035x - 000 rev. 1.2 final
EM351 / em357 adc_dmastat adc dma status register address: 0x4000d014 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 adc_dmaovf adc_dmaact bitname bitfield access description adc_dmaovf [1] r dma overflow: occurs when an adc result is ready and the dma is not active. cleared by dma re set. adc_dmaact [0] r dma status: reads 1 if dma is active. 10- 18 120 - 035x - 000 rev. 1.2 final
EM351 / em357 adc_dmabeg adc dma begin address register address: 0x4000d018 reset: 0x20000000 31 30 29 28 27 26 25 24 0 0 1 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 adc_dmabeg 7 6 5 4 3 2 1 0 adc_dmabeg bitname bitfield access description adc_dmabeg [ 13 :0] rw adc buffer start address. caution: this must be an even address - the least significant bit of this register is fixed at zero by hardware. 10- 19 120 - 035x - 000 rev. 1.2 final
EM351 / em357 adc_dmasize adc dma buffer size register address: 0x4000d01c reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 adc_dmasize_field 7 6 5 4 3 2 1 0 adc_dmasize_field bitname bitfield access description adc_dmasize_field [ 12 :0] rw adc buffer size. this is the number of 16 - bit adc conversion results the buffer can hold, not its length in bytes. (the length in bytes is twice this value.) 10- 20 120 - 035x - 000 rev. 1.2 final
EM351 / em357 adc_dmacur adc dma current address register address: 0x4000d020 reset: 0x20000000 31 30 29 28 27 26 25 24 0 0 1 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 adc_dmacur_field 7 6 5 4 3 2 1 0 adc_dmacur_field 0 bitname bitfield access description adc_dmacur_field [1 3 :1] r current dma address: the location that will be written next by the dma. 10- 21 120 - 035x - 000 rev. 1.2 final
EM351 / em357 adc_dmacnt adc dma count register address: 0x4000d024 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 adc_dmacnt_field 7 6 5 4 3 2 1 0 adc_dmacnt_field bitname bitfield access description adc_dmacnt_field [ 12 :0] r dma count: the number of 16 - bit conversion results that have been written to the buffer. 10- 22 120 - 035x - 000 rev. 1.2 final
EM351 / em357 int_adcflag adc interrupt flag register address: 0x4000a810 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 int_adcovf i n t _ a d cs at int_adculdfull int_adculdhalf int_adcflagrsvd bitname bitfield access description int_adcovf [4] rw dma buffer overflow interrupt pending. in t_ adc s at [3] rw gain correction saturation interrupt pending. int_adculdfull [2] rw dma buffer full interrupt pending. int_adculdhalf [1] rw dma buffer half full interrupt pending. int_ adcdata [0] rw adc_data register has data interrupt pending. 10- 23 120 - 035x - 000 rev. 1.2 final
EM351 / em357 int_adccfg adc interrupt configuration register address: 0x4000a850 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 int_adcovf i n t _ a d cs at int_adculdfull int_adculdhalf int_adccfgrsvd bitname bitfield access description int_adcovf [4] rw dma buffer overflow interrupt enable. in t_ adc s at [3] rw gain correction saturation interrupt enable. int_adculdfull [2] rw dma buffer full interrupt enable. int_adculdhalf [1] rw dma buffer half full interrupt enable. int_ adcdata [0] rw adc_data register has data interrupt enable. 10- 24 120 - 035x - 000 rev. 1.2 final
EM351 / em357 11 interrupt system the em35x ?s interrupt system is composed of two parts: a standard arm ? cortex tm - m3 nested vectored interrupt controller (nvic) that provides top - level interrupts , and a proprietary event manager (em) that provides second - level interrupts. the nvic and e m provide a simple hierarchy. all second - level interrupts from the em feed into top - level interrupts in the nvic. this two - level hierarchy allows for both fine granular c ontrol of interrupt sources and coarse granular control over entire peripherals , while allowing peripherals to have their own interrupt vector. the nested vector ed interrupt controller (nvic) section provides a description of the nvic and an overview of the exception table (arm nomenclature refers to interrupts as exceptions) . t he event manage r section provides a more detailed description of the event manager including a table of all top - level peripheral interrupts and their second - level interrupt sources. in practice, top - level peripheral interrupts are only used to enable or disable interrupt s for an entire peripheral . second - level interrupts originate from hardware sources , and therefore are the main focus of applications using interrupts. 11.1 nested vector ed interrupt controller (nvic) the arm ? cortex tm - m3 nested vectored interrupt controller (nvic) facilitates low - latency exception and interrupt handling . the nvic and the processor core interface are closely coupled, which enables low - latency interrupt processing a nd efficient p rocessing of late - arriving interrupts. the nvic also maintains knowledge of the stacked (nested) interrupts to enable tail - chaining of interrupts. the arm ? cortex tm - m3 nvic contains 10 standard interrupts that are related to chip and cpu operation and mana gement. in addition to the 10 standard interrupts, it contains 17 individually vectored peripheral interrupts specific to the em35x . the nvic defines a list of exceptions. these exceptions include not only traditional peripheral interrupts, but also more s pecialized events such as faults and cpu reset. in the arm ? cortex tm - m3 nvic, a cpu reset event is considered an exception of the highest priority , and the stack pointer is loaded from the first position in the nvic exception table. the nvic exception tabl e defines all exce ptions and their position , including peripheral interrupts . t he position of each exception is important since it directly translates to the location of a 32 - bit interrupt vector for each interrupt , and defines the hardware priority of exceptions . each exception in the table is a 32 - bit address that is loaded into the program counter when that exception occurs. table 11- 1 lists the entire exception table. exceptions 0 (stack pointer) through 15 (systick) are part of the standard arm ? cortex tm - m3 nvic , while exceptions 16 (timer 1) through 32 (debug) are the peripheral interrupts specific to the em35x peripherals . the peripheral interrupts are listed in greater detail in table 11 - 2 . 11- 1 120 - 035x - 000 rev. 1.2 final
EM351 / em357 table 11- 1 . nvic exception table exception position description - 0 stack top is loaded from first entry of vector table on reset. reset 1 invoked on power up and warm reset. on first instruction, drops to lowest priority (thread mode). a synchronous. nmi 2 cannot be stopped or preempted by any exception but reset. a synchronous. hard fault 3 all classes of fault , when the fault cannot activa te because of priority or the configurable fault handler has been disabled. s ynchronous. memory fault 4 mpu mismatch, including access violation and no match. s ynchronous. bus fault 5 pre - fetch, memory access, and other address/memory - related faults . s ynchronous when precise and asynchronous when imprecise. usage fault 6 usage fault, such as ? u ndefined instruction executed ? or ? illegal state transition attempt ? . s ynchronous. - 7 - 10 reserved . svcall 11 system service call with svc instruction. s ynchronous. debug monitor 12 debug monitor, when not halting. s ynchronous, but only active when enabled. it does not activate if lower priority than the current activation. - 13 reserved . pendsv 14 pendable request for system service. a synchronous and only pended by software. systick 15 system tick timer has fired. a synchronous. timer 1 16 timer 1 peripheral interrupt. timer 2 17 timer 2 peripheral interrupt. management 18 management peripheral interrupt. baseb and 19 baseband peripheral interrupt. sleep timer 20 sleep timer peripheral interrupt. serial controller 1 21 serial controller 1 peripheral interrupt. serial controller 2 22 serial controller 2 peripheral interrupt. security 23 security peripheral interrupt. mac timer 24 mac timer peripheral interrupt. mac transmit 25 mac transmit peripheral interrupt. mac receive 26 mac receive peripheral interrupt. adc 27 adc peripheral interrupt. irqa 28 irqa peripheral interrupt. irqb 29 irqb peripheral interrupt. irqc 30 irqc peripheral interrupt. irqd 31 irqd peripheral interrupt. debug 32 debug peripheral interrupt. 11- 2 120 - 035x - 000 rev. 1.2 final
EM351 / em357 the nvic also contains a software - configurable interrupt prioritization mechanism. the reset, nmi, and hard fault exceptions , in that order, are always the highest priority, and are not software - configurable . all other exceptions c an be assigned a 5 - bit priority number , with low values representing higher priority. if any exceptions have the same software - configurable priority, then the nvic uses the hardware - defined priority. the hardware - defined priority number is the same as the position of the exception in the exception table. for example, if irqa and irqb both fire at the same time and have the same software - define d priority , t he nvic handle s irqa , with priority number 28, first because it has a higher hardware priority than irqb with priority number 29. the top - level interrupts are controlled through five arm ? cortex tm - m3 nvic registers : int_cfgset, int_cfgclr, int_pendset, int_pendclr, and int_active. writing 0 into any bit in any of these five register is ineffective . ? int_cfgset - writing 1 to a bit in int_cfgset enable s that top - level interrupt. ? int_cfgclr - writing 1 to a bit in int_cfgclr disable s that top - level interrupt. ? int_pendset - writing 1 to a bit in int_pendset trigger s that top - level interrupt. ? int_pendclr - writing 1 to a bit in int_pendclr clear s that top - level interrupt. ? int_active cannot be written to and is used for indicating which interrupts are currently active. i nt_pendset and int_pendclr set and clear a simple latch ; int_cfgset and int_cfgclr set and clear a mask on the output of the latch. i nterrupts may be pended and cleared at any time, but any pended interrupt will not be taken unless the corresponding mask ( int_cfgset) is set , which allows that interrupt to propagate. if an int_cfgset bit is set and the corresponding int_pendset bit is set, then the interrupt will propagate and be taken. if int_cfgset is set after int_pendset is set, then the interrupt will a lso propagate and be taken. interrupt flags (signals) from the top - level interrupts are level - sensitive. the second - level interrupt registers , which provide control of the second - level event manager peripheral interrupts , are described in the event manager section. for further information on the nvic and arm ? cortex tm - m3 exceptions, refer to the arm ? cortex tm - m3 technical reference manual an d the arm armv7 - m architecture reference manual. 11.2 event manager while the standard arm ? cortex tm - m3 nested vectored interrupt controller provides top - level interrupts into the cpu, the proprietary event manager provides second - level interrupts . the event ma nager take s a large variety of hardware interrupt sources from the peripherals and merge s them into a smaller group of interrupts in the nv ic. effectively, all second - level interrupts from a peripheral are ?or? d ? together into a single interrupt in the nvic. in addition, the event manager provides missed indicators for the top - level peripheral interrupts with the register int_miss . the description of each peripheral?s interrupt configuration and flag registers c an be found in the chapters of this datasheet describing each peripheral. figure 11 - 1 shows the peripheral interrupts block diagram. 11- 3 120 - 035x - 000 rev. 1.2 final
EM351 / em357 figure 11 - 1 . peripheral interrupts block diagram q latch s r read q latch s r write 1 read and write 1 q latch s r write 1 write 1 interrupts into nvic / cpu int _ pendset int _ pendclr int _ cfgset int _ cfgclr int _ miss source interrupt events q latch s r write 1 read and or int _ periphcfg int _ periphflag read or write 1 peripheral interrupt instance interrupts from all peripherals and or given a peripheral, ?periph?, the event manager regis ters ( int_periphcfg and int_periphflag ) follow the form: ? int_periphcfg enables and disables second - level interrupt s . writing 1 to a bit in the int_periphcfg register enables the second - level interrupt . w riting 0 to a bit in the int_periphcfg register disables it . the int_periphcfg register behaves like a mask , and is responsible for allowing the int_periphfla g bits to propagate into the top - level nvic interrupts. ? int_periphflag indicates second - level interrupts that have occurred. writing 1 to a bit in a int_periphflag register clears the second - level interrupt. writing 0 to any bit in the int_periphflag register is ineffective . the int_periphflag register is always active and may be set or cleared at any time , meaning if any second - level interrupt occurs, then the corresponding bit in the int_periphflag register is set regardless of the state of int_peri phcfg . i f a bit in the int_periphcfg register is set after the corresponding bit in the int_periphflag register is set then the second - level interrupt propagate s into the top - level interrupts. the interrupt flags (signals) from the second - level interrupts into the top - level interrupts are level - sensitive. if a top - level nvic interrupt is driven by a second - level em interrupt, then the top - level nvic interrupt cannot be cleared until all second - level em interrupts are cleared. the int_periphflag register bits are designed to remain set if the second - level interrupt event re - occurs at the same moment as the int_periphflag register bit is being cleared . this ensures the re - occurring second - level inter rupt event is not missed. if another enabled second - level interrupt event of the same type occurs before the first interrupt event is cleared, the second interrupt event is lost because no counting or queuing is used. however, this condition is detected and stored in the top - level int_miss register to facilitate software detection of such problems. the int_miss register is ?acknowledged? in the same way as the int_periphflag register ? by writing a 1 into the corresponding bit to be cleared. table 11 - 2 provides a map of all peripheral interrupts. this map lists the top - level nvic interrupt bits and, if there is one, the corresponding second - level em interrupt register bits that feed the top - level interrupts. 11- 4 120 - 035x - 000 rev. 1.2 final
EM351 / em357 table 11- 2 . nvic and em peripheral interrupt map nvic interrupt (top - level) em interrupt (second - level) nvic interrupt (top - level) em interrupt (second - level) 16 int_debug 5 int_sc1 int_sc1flag register 15 int_irqd 14 int_sc1parerr 14 int_irqc 13 int_sc1frmerr 13 int_irqb 12 int_sctxuldb 12 int_irqa 11 int_sctxulda 11 int_adc int_adcflag register 10 int_scrxuldb 4 int_adcovf 9 int_scrxulda 3 int_adcsat 8 int_scnak 2 int_adculdfull 7 int_sccdmfin 1 int_adculdhalf 6 int_sctxfin 0 int_adcdata 5 int_scrxfin 10 int_macrx 4 int_sctxund 9 int_mactx 3 int_scrxovf 8 int_mactmr 2 int_sctxidle 7 int_sec 1 int_sctxfree 6 int_sc2 int_sc2flag register 0 int_scrxval 12 int_sctxuldb 4 int_sleeptmr 11 int_sctxulda 3 int_bb 10 int_scrxuldb 2 int_mgmt 9 int_scrxulda 1 int_tmr2 int_tmr2flag register 8 int_scnak 6 int_tmrtif 7 int_sccdmfin 4 int_tmrcc4if 6 int_sctxfin 3 int_tmrcc3if 5 int_scrxfin 2 int_tmrcc2if 4 int_sctxund 1 int_tmrcc1if 3 int_scrxovf 0 int_tmruif 2 int_sctxidle 0 int_tmr1 int_tmr1flag register 1 int_sctxfree 6 int_tmrtif 0 int_scrxval 4 int_tmrcc4if 3 int_tmrcc3if 2 int_tmrcc2if 1 int_tmrcc1if 0 int_tmruif 11- 5 120 - 035x - 000 rev. 1.2 final
EM351 / em357 11.3 non - maskable interrupt ( nmi ) the non - maskable interrupt (nmi) is a special case . d espite being one of the 10 standard arm ? cortex tm - m3 nvic interrupts, it is sourced from the event manager like a peripheral interrupt. the nm i has two second - level sources ; f ailure of the 24 mhz crystal and watchdog low water mark. 1. failure of the 24mhz crystal : if the em35x ?s main clock, s ys clk, is operating from the 24 mhz crystal and the crystal fails, the em35x de tect s the failure and automatically switch es to the internal 12 mhz rc clock. when this failure detection and switch has occurred, the em35x trigger s the clk24m_fail second - level interrupt , which then trigger s the nmi. 2. watchdog low water mark: if the em35 x ?s watchdog is active and the watchdog counter has not been reset for nominally 1.792 seconds, the watchdog trigger s the watchdog_int second - level interrupt , which then trigger s the nmi. 11.4 faults four of the exceptions in the nvic are faults: hard fault, memory fault, bus fault, and usage fault. of these , three (hard fault, memory fault, and usage fault) are standard arm ? cortex tm - m3 exceptions . the bus fault, though, is derived from em35x - specific sources. the bus fault sources are recorded in the scs_afsr register. note that it is possible for one access to set multiple scs_afsr bits. also note that mpu configurations could prevent most of these bus fault accesses from occurring , with the advantag e that illegal writes are made precise faults. the four bus faults are: ? wrongsize ? generated by an 8 - bit or 16 - bit read or write of an apb peripheral register. this fault can also result from an unaligned 32 - bit access. ? protected ? generated by a user mod e (unprivileged) write to a system apb or ahb peripheral or protected ram (see chapter 5, s ection 5.2.2.3) . ? reserved ? generated by a read or write to an address within an apb peripheral?s 4 kb block range, but the address is above the last physical regist er in that block range. also generated by a read or write to an address above the top of ram or flash. ? missed ? generated by a second scs_afsr fault. in practice, this bit is not seen since a second fault also generate s a hard fault , and the hard fault preempt s the bus fault. 11- 6 120 - 035x - 000 rev. 1.2 final
EM351 / em357 11.5 registers int_cfgset to p - level set interrupts configuration register address: 0xe000e100 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 int_debug 15 14 13 12 11 10 9 8 int_irqd int_irqc int_irqb int_irqa int_adc int_macrx int_mactx int_mactmr 7 6 5 4 3 2 1 0 int_sec int_sc2 int_sc1 int_sleeptmr int_bb int_mgmt int_tim2 int_tim1 bitname bitfield access description int_debug [16] rw write 1 to enable debug interrupt. (writing 0 has no effect.) int_irqd [15] rw write 1 to enable irqd interrupt. (writing 0 has no effect.) int_irqc [14] rw write 1 to enable irqc interrupt. (writing 0 has no effect.) int_irqb [13] rw write 1 to enable irqb interrupt. (writing 0 has no effect.) int_irqa [12] rw write 1 to enable irqa interrupt. (writing 0 has no effect.) int_adc [11] rw write 1 to enable adc interrupt. (writing 0 has no effect.) int_macrx [10] rw write 1 to enable mac receive interrupt. (writing 0 has no effect.) int_mactx [9] rw write 1 to enable mac transmit interrupt. (writing 0 has no effect.) int_mactmr [8] rw write 1 to enable mac timer interrupt. (writing 0 has no effect.) int_sec [7] rw write 1 to enable security interrupt. (wr iting 0 has no effect.) int_sc2 [6] rw write 1 to enable serial controller 2 interrupt. (writing 0 has no effect.) int_sc1 [5] rw write 1 to enable serial controller 1 interrupt. (writing 0 has no effect.) int_sleeptmr [4] rw write 1 to enable sleep timer interrupt. (writing 0 has no effect.) int_bb [3] rw write 1 to enable baseband interrupt. (writing 0 has no effect.) int_mgmt [2] rw write 1 to enable management interrupt. (writing 0 has no effect.) int_tim2 [1] rw write 1 to enable timer 2 interrupt. (writing 0 has no effect.) int_tim1 [0] rw write 1 to enable timer 1 interrupt. (writing 0 has no effect.) 11- 7 120 - 035x - 000 rev. 1.2 final
EM351 / em357 int_cfgclr to p - level clear interrupts configuration register address: 0xe000e180 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 int_debug 15 14 13 12 11 10 9 8 int_irqd int_irqc int_irqb int_irqa int_adc int_macrx int_mactx int_mactmr 7 6 5 4 3 2 1 0 int_sec int_sc2 int_sc1 int_sleeptmr int_bb int_mgmt int_tim2 int_tim1 bitname bitfield access description int_debug [16] rw write 1 to disable debug interrupt. (writing 0 has no effect.) int_irqd [15] rw write 1 to disable irqd interrupt. (writing 0 has no effect.) int_irqc [14] rw write 1 to disable irqc interrupt. (writing 0 has no effect.) int_irqb [13] rw write 1 to disable irqb interrupt. (writing 0 has no effect.) int_irqa [12] rw write 1 to disable irqa interrupt. (writing 0 has no effect.) int_adc [11] rw write 1 to disable adc interrupt. (writing 0 has no effect.) int_macrx [10] rw write 1 to disable mac receive interrupt. (writing 0 has no effect.) int_mactx [9] rw write 1 to disable mac transmit interrupt. (writing 0 has no effect.) int_mactmr [8] rw write 1 to disable mac timer interrupt. (writing 0 has no effe ct.) int_sec [7] rw write 1 to disable security interrupt. (writing 0 has no effect.) int_sc2 [6] rw write 1 to disable serial controller 2 interrupt. (writing 0 has no effect.) int_sc1 [5] rw write 1 to disable serial controller 1 interrupt. (writing 0 has no effect.) int_sleeptmr [4] rw write 1 to disable sleep timer interrupt. (writing 0 has no effect.) int_bb [3] rw write 1 to disable baseband interrupt. (writing 0 has no effect.) int_mgmt [2] rw write 1 to disable management interrupt. (writing 0 has no effect.) int_tim2 [1] rw write 1 to disable timer 2 interrupt. (writing 0 has no effect.) int_tim1 [0] rw write 1 to disable timer 1 interrupt. (writing 0 has no effect.) 11- 8 120 - 035x - 000 rev. 1.2 final
EM351 / em357 int_pendset to p - level set interrupts pending register address: 0xe000e200 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 int_debug 15 14 13 12 11 10 9 8 int_irqd int_irqc int_irqb int_irqa int_adc int_macrx int_mactx int_mactmr 7 6 5 4 3 2 1 0 int_sec int_sc2 int_sc1 int_sleeptmr int_bb int_mgmt int_tim2 int_tim1 bitname bitfield access description int_debug [16] rw write 1 to pend debug interrupt. (writing 0 has no effect.) int_irqd [15] rw write 1 to pend irqd interrupt. (writing 0 has no effect.) int_irqc [14] rw write 1 to pend irqc interrupt. (writing 0 has no effect.). int_irqb [13] rw write 1 to pend irqb interrupt. (writing 0 has no effect.) int_irqa [12] rw write 1 to pend irqa interrupt. (writing 0 has no effect.) int_adc [11] rw write 1 to pend adc in terrupt. (writing 0 has no effect.) int_macrx [10] rw write 1 to pend mac receive interrupt. (writing 0 has no effect.) int_mactx [9] rw write 1 to pend mac transmit interrupt. (writing 0 has no effect.) int_mactmr [8] rw write 1 to pend mac timer interrupt. (writing 0 has no effect.) int_sec [7] rw write 1 to pend security interrupt. (writing 0 has no effect.) int_sc2 [6] rw write 1 to pend serial controller 2 interrupt. (writing 0 has no effect.) int_sc1 [5] rw write 1 to pend serial controller 1 interrupt. (writing 0 has no effect.) int_sleeptmr [4] rw write 1 to pend sleep timer interrupt. (writing 0 has no effect.) int_bb [3] rw write 1 to pend baseband interrupt. (writing 0 has no effect.) int_mgmt [2] rw write 1 to pend management interrupt. (writing 0 has no effect.) int_tim2 [1] rw write 1 to pend timer 2 interrupt. (writing 0 has no effect.) int_tim1 [0] rw write 1 to pend timer 1 interrupt. (writing 0 has no effect.) 11- 9 120 - 035x - 000 rev. 1.2 final
EM351 / em357 int_pendclr to p - level clear interrupts pending register add ress: 0xe000e280 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 int_debug 15 14 13 12 11 10 9 8 int_irqd int_irqc int_irqb int_irqa int_adc int_macrx int_mactx int_mactmr 7 6 5 4 3 2 1 0 int_sec int_sc2 int_sc1 int_sleeptmr int_bb int_mgmt int_tim2 int_tim1 bitname bitfield access description int_debug [16] rw write 1 to unpend debug interrupt. (writing 0 has no effect.) int_irqd [15] rw write 1 to unpend irqd interrupt. (writing 0 has no effect.) int_irqc [14] rw write 1 to unpend irqc interrupt. (writing 0 has no effect.) int_irqb [13] rw write 1 to unpend irqb interrupt. (writing 0 has no effect.) int_irqa [12] rw write 1 to unpend irqa interrupt. (writing 0 has no effect.) int_adc [11] rw wri te 1 to unpend adc interrupt. (writing 0 has no effect.) int_macrx [10] rw write 1 to unpend mac receive interrupt. (writing 0 has no effect.) int_mactx [9] rw write 1 to unpend mac transmit interrupt. (writing 0 has no effect.) int_mactmr [8] rw write 1 to unpend mac timer interrupt. (writing 0 has no effect.) int_sec [7] rw write 1 to unpend security interrupt. (writing 0 has no effect.) int_sc2 [6] rw write 1 to unpend serial controller 2 interrupt. (writing 0 has no effect.) int_sc1 [5] rw write 1 to unpend serial controller 1 interrupt. (writing 0 has no effect.) int_sleeptmr [4] rw write 1 to unpend sleep timer interrupt. (writing 0 has no effect.) int_bb [3] rw write 1 to unpend baseband interrupt. (writing 0 has no effect.) int_mgmt [2] rw write 1 to unpend management interrupt. (writing 0 has no effect.) int_tim2 [1] rw write 1 to unpend timer 2 interrupt. (writing 0 has no effect.) int_tim1 [0] rw write 1 to unpend timer 1 interrupt. (writing 0 has no effect.) 11- 10 120 - 035x - 000 rev. 1.2 final
EM351 / em357 int_active to p - level active interrupts register address: 0xe000e300 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 int_debug 15 14 13 12 11 10 9 8 int_irqd int_irqc int_irqb int_irqa int_adc int_macrx int_mactx int_mactmr 7 6 5 4 3 2 1 0 int_sec int_sc2 int_sc1 int_sleeptmr int_bb int_mgmt int_tim2 int_tim1 bitname bitfield access description int_debug [16] r debug interrupt active. int_irqd [15] r irqd interrupt active. int_irqc [14] r irqc interrupt active. int_irqb [13] r irqb interrupt active. int_irqa [12] r irqa interrupt active. int_adc [11] r adc interrupt active. int_macrx [10] r mac receive interrupt active. int_mactx [9] r mac transmit interrupt active. int_mactmr [8] r mac timer interrupt active. int_sec [7] r security interrupt active. int_sc2 [6] r serial controller 2 interrupt active. int_sc1 [5] r serial controller 1 interrupt active. int_sleeptmr [4] r sleep timer interrupt active. int_bb [3] r baseband interrupt active. int_mgmt [2] r management interrupt active. int_tim2 [1] r timer 2 interrupt active. int_tim1 [0] r timer 1 interrupt active. 11- 11 120 - 035x - 000 rev. 1.2 final
EM351 / em357 int_miss to p - level missed interrupts register address: 0x4000a820 reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 int_missirqd int_missirqc int_missirqb int_missirqa int_missadc int_missmacrx int_missmactx int_missmactmr 7 6 5 4 3 2 1 0 int_misssec int_misssc2 int_misssc1 int_misssleep int_missbb int_missmgmt 0 0 bitname bitfield access description int_missirqd [15] rw irqd interrupt missed. int_missirqc [14] rw irqc interrupt missed. int_missirqb [13] rw irqb interrupt missed. int_missirqa [12] rw irqa interrupt missed. int_missadc [11] rw adc interrupt missed. int_missmacrx [10] rw mac receive interrupt missed. int_missmactx [9] rw mac transmit interrupt missed. int_missmactmr [8] rw mac timer interrupt missed. int_misssec [7] rw security interrupt missed. int_misssc2 [6] rw serial controller 2 interrupt missed. int_misssc1 [5] rw serial controller 1 interrupt missed. int_misssleep [4] rw sleep timer interrupt missed. int_missbb [3] rw baseband interrupt missed. int_missmgmt [2] rw management interrupt missed. 11- 12 120 - 035x - 000 rev. 1.2 final
EM351 / em357 scs_afsr auxiliary fault status register address: 0xe000ed3c reset: 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 wrongsize protected reserved missed bitname bitfield access description wrongsize [3] rw a bus fault resulted from an 8 - bit or 16 - bit read or write of an apb peripheral register. this fault can also result from an unaligned 32 - bit access. protected [2] rw a bus fault resulted from a user mode (unprivileged) write to a system apb or ahb peripheral or protected ram. reserved [1] rw a bus fault resulted from a read or write to an address within an apb peripheral's 4 kb block range, but above the last physical register in that block. can also result from a read or write to an address above the top of ram or flash. missed [0] rw a bus fault occurred when a bit was already set in this register. 11- 13 120 - 035x - 000 rev. 1.2 final
EM351 / em357 12 trace port interface unit (tpiu) the em35x integrates the standard arm ? trace port interface unit (tpiu). the tpiu receives a data stream from the on - chip trace data generated by the standard arm ? instrument trace macrocell (itm) , buffers the data in a fifo , formats the data, and serializes the data to be sent off chip throug h alternate functions of the gpio. since the primary function of the tpiu is to provide a bridge between on - chip arm system debug components and external gpio, the tpiu itself does not generat e data. figure 12- 1 illustrates the three primary components of the tpiu . figure 12 - 1 . tpiu block diagram asynchronous fifo formatter itm trace out (serializer) traceclk tracedata2 tracedata3 tracedata1 tracedata0 swo the tpiu is comp o sed of: ? asynchronous fifo: the asynchronous fifo receives a data stream generated by the itm and enables the trace data to be sent off chip at a speed that is not dependent on the speed of the data source. ? formatter: the formatter inserts source id signals into the data packet stream so that trace data can be re - associated with its trace source. since the em35x has only one trace source, the itm, it is not necessary to use the formatter and therefore the formatter only adds overhead into the data stream . since c ertain modes of the tpiu a utomati cally enable the formatter, these modes should be avoided whenever possible. ? trace out: the trace out block serializes the data and sends it off chip by the proper alternate output gpio functions. the five pins available to the tpiu are: ? swo ? tracec lk ? tracedata0 ? tracedata1 ? tracedata2 ? tracedata3 since these pins are alternate outputs of gpio, refer to chapter 1, pin assignments and chapter 7, gpio for complete pin descriptions and configurations. note: the swo alternate output i s mirrored on gpio pc1 and pc2. note: gpio pc1 shares both the swo and tracedata0 alternate outputs. this is possible because swo and tracedata0 are mutually exclusive and only one may be selected at a time in the trace out block. t he ember software utilizes the tpiu for eff iciently outpu tting debug data . a ltering the tpiu configuration may conflict with ember debug output. for further information on the tpiu, contact silicon labs support for the arm ? cortex tm - m3 technical reference manual, the arm ? coresight tm compon ents technical reference manual, the arm ? v7 - m a rchitecture reference manual, and the arm ? v7 - m architecture application level reference manual. 12- 1 120 - 035x - 000 rev. 1.2 final
EM351 / em357 13 instrumentation trace macrocell (itm) the em35x integrates the standard arm ? instrumentation trace macrocell (itm). the itm is an application - driven trace source that supports printf style debugging to trace software events and emits diagnostic system information from the arm ? data watchpoint and trace (dwt) . softwa re using the itm generates softw are instrumentation trace (swit). in addition, the itm provides coarse - grained timestamp functionality. the itm emits trace information as packets, and these packets are sent to the trace port interface unit (tpiu). t hree sources can generate packets. if multiple sources generate packets at the same time, the itm arbitrates the order in which the packets are output. the three sources, in decreasing order of priority, are: ? software trace. software can write directly to itm stimulus registers, emitting packets. ? hardware trace. the dwt generates packets that the itm emits. ? time stamping. timestamp s ar e emitted relative to packets and t he itm contains a 21 - bit counter to generate the timestamps. the ember software utilizes the itm for efficiently generating debug data. altering the itm configuration may conflict with ember debug output. for further information on the itm, contact silicon labs support for the arm ? cortex tm - m3 technical reference manual, the arm ? coresight tm components technical reference manual, the arm ? v7 - m architecture reference manual, and the arm ? v7 - m architecture application level reference manual. 13- 1 120 - 035x - 000 rev. 1.2 final
EM351 / em357 14 data watchpoint and trace ( dwt ) the em35x integrates the standard arm ? data watchpoint and trace (dwt). the dwt provides hardware support for profiling and debugging functionality. the dwt offers the following features: ? pc sampling ? comparators to support: ? watchpoints ? enters debug state ? data tracing ? cycle count matched pc sampling ? exception trace support ? instruction cycle count calculation support apart from exception tracing, dwt functionality is counter - or comparator - based. watchpoint and data trace support use a set of compare, mask, and function registers. dwt - generated events result in one of two actions: ? generation of a hardware event packet. packets are generated and combin ed with software events and timestamp packets for transmission through the itm/ tpiu. ? a core halt ? entry to debug state. when exception tracing is enabled, the dwt emits an exception trace packet under the following conditions: ? exception entry (from threa d mode or pre - emption of a thread or handler). ? exception exit when exiting a handler. ? exception return when re - entering a pre - empted thread or handler code sequence. the dwt is designed for use with advanced profiling and debug tools, available from multiple vendors. altering dwt configuration may conflict with the operation of advanced profiling and debug tools. for further information on the dwt , contact silicon labs support for the arm ? cortex tm - m3 technical reference manual, the arm ? coresight tm components technical reference manual, the arm ? v7 - m architecture reference manual, and the arm ? v7 - m architecture application level reference manual. 14- 1 120 - 035x - 000 rev. 1.2 final
EM351 / em357 15 flash patch and breakpoint ( fpb ) the em35x integrates the standard arm ? flash patch and breakpoint ( fpb ). the fpb implements hardware b r eakpoints. the fpb also provides support for remapping of specific instruction or literal locations from flash memory to an address in ram memory. the fpb contains: ? two literal comparators for matching against literal loads from flash space, and remapping to a corresponding ram space. ? si x instruction comparators for matching against instruction fetches from flash space, and remapping to a corresponding ram space. alternatively, the comparators can be individually configured to return a b reakpoint i nstruction to the processor core on a match, implement ing hardware breakpoint capability. the fpb contains a global enable, but also individual enables for the eight comparators. if the comparison for an entry matches, the address is remapped to the address defined in the remap register plus and offset corre sponding to the comparator that matched. alternately, the address is remapped to a breakpoint instruction. the comparison happens on the fly, but the result of the comparison occurs too late to stop the original instruction fetch or literal load taking pla ce from the flash space. the processor ignores this transaction, however, and only the remapped transaction is used. memory p rotection u nit (mpu) lookups are performed for the original address, not the remapped address. unaligned literal accesses are not r emapped. the original access to the bus takes place in this case. the fpb is designed for use with advanced debug tools, available from multiple vendors. altering fpb configuration may conflict with the operation of advanced debug tools. for further inform ation on the fpb , contact silicon labs support for the arm ? cortex tm - m3 technical reference manual, the arm ? coresight tm components technical reference manual, the arm ? v7 - m architecture reference manual, and the arm ? v7 - m architecture application level reference manual. 15- 1 120 - 035x - 000 rev. 1.2 final
EM351 / em357 16 integrated voltage regulator the em35x integrates two low dropout regulator s to provide 1.8 v and 1.25 v power supplies , as detailed in table 16 - 1 . t he 1 v 8 regulator supplies the analog and memories, and the 1 v 25 regulator supplies the digital core. in d eep s leep the voltage regulators are disabled. when enable d, the 1 v 8 regulator steps down the pa ds supply voltage ( vdd_pads ) from a nominal 3.0 v to 1.8 v . the regulator output pin ( vreg_out ) must be decoupled externally with a suitable capacitor. vreg_out should be connected to the 1 .8 v supply pins vdd a , vdd_rf, vdd_vco, vdd_synth, vdd_if, and vdd_mem . the 1 v 8 regulator can supply a maximum of 50 ma. when enabled , the 1 v 25 regulator steps down vdd_pads to 1.25 v . the regulator output pin ( vdd_core , pin 17) must be decoupled externally with a suitable capacitor. it should connect to the other vdd_core pin ( p in 44) . the 1 v 25 regulator can supply a maximum of 10 ma. the regulators are controlled by the digital portion of the chip as described in chapter 6 , system modules . an example of decoupling capacitors and pcb layout can be found in the application note s ( see the various silicon labs em35x r eference d esign documentation ). table 16- 1 . integrated voltage regulator specifications spec point min. typ. max. units comments supply range for regulator 2.1 3.6 v vdd_pads 1 v 8 r egulator output - 5% 1.8 +5% v regulator output after initialization 1v8 r egul ator output after reset - 5% 1. 75 +5% regulator output after reset 1v25 r egulator output - 5% 1. 25 +5% v regulator output after initialization 1v25 r egul ator output after reset - 5% 1.45 +5% regulator output after reset 1 v 8 regulator capacitor 2.2 f low esr t antalum capacitor esr greater than 2 esr less than 10 de - coupling less than 100 nf ceramic 1v25 regulator capacitor 1.0 f ceramic capacitor (0603) 1v8 regulator output current 0 50 ma regulator output current 1v25 regulator output current 0 1 0 ma regulator output current no load c urrent 6 00 a no load cu rrent (bandgap and regulator s ) 1v8 regulator current limit 200 ma short circuit c urrent limit 1v25 regulator current limit 25 ma short circuit c urrent limit 1v8 regulator start - up time 50 s 0 v to por threshold 2.2 f capacitor 1v25 regulator start - up time 50 s 0 v to por threshold 1.0 f capacitor 16- 1 120 - 035x - 000 rev. 1.2 final
EM351 / em357 a n external 1.8 v regulator may replace both internal regulators . the em35x can control external regulators d uring deep sleep using open - drain gpio pa7 , as described in chapter 7, gpio . the em35x drives pa7 low during deep sleep to disable the external regulator and a n external pull - up is required to release this si gnal to indicate that supply voltage should be provided. c urrent consumption increases approximately 2 ma when using an external regulator. when using an external regulator the internal regula tors should be disabled through ember software. the always - on domain needs to be minimally powered at 2.1 v, and cannot be powered from the external 1.8 v regulator. 16- 2 120 - 035x - 000 rev. 1.2 final
EM351 / em357 17 serial wire and jtag (swj) interface the em35x includes a standard serial wire and jtag (swj) interface. the swj is the primary debug and programming interface of the em35x . the swj gives debug tools access to the internal buses of the em35x , and allows for non - intrusive memory and register access as well as cpu halt - step style debugging. therefore, any design implementing the em35x should make the swj signals readily availabl e. serial wire is an arm? standard, bi directional, two - wire protocol designed to replace jtag, and provides all the normal jtag debug and test functionality. jtag is a standard five - wire protocol providing debug and test functionality. in addition, the two serial wire signals (swdio and swclk) are overlaid on two of the jtag signals (jtms and jtck) . this keeps the design compact and allows debug tools to switch between serial wire and jtag as needed , without changing pin connections. while serial wire and jtag offer the same debug and test functionality, silicon labs recommends serial wire. serial wire uses only two pins instead of five, and offers a simple communication protocol, high performance data rates, low power, built - in error detection, and protection from glitches. the arm? coresight tm debug access port (dap) comprises the serial wire and jtag interface (swj) . as illustrated in figure 17- 1 , t he dap includes two primary components: a d ebug p ort ( the swj - dp ) and an a ccess p ort ( the ahb - ap ) . the swj - dp provides external debug access, while the ahb - ap provide s internal bus access. an external debug tool connected to the em35x ?s debug pins communicates with the swj - dp . the swj - dp then communicates with the ahb - ap . finally, the ahb - ap communicates on the internal bus. figure 17 - 1 . swj block diagram swj-dp swj-dp select swj-dap sw interface jtag interface control and ap interface pins ahb-ap ahb serial wire and jt ag share five pins : ? jrst ? jtdo ? jtdi ? swdio/jtms ? swclk / jtck note: the swj pins are forced functions , and their corresponding gpio_pxcfgh/l configuration s are overridden when the em35x resets. a n application must disable all debug swj debug functionality to reclai m any of the four swj gpio s : pc0, pc2, pc3, and pc4 . since these pins can be repurposed, refer to chapter 1, pin assignments , and section 7.3, forced functions , in chapter 7, gpio, fo r complete pin descriptions and configurations. for further information on the swj, contact customer support for application notes and arm ? coresight tm documentation. 17- 1 120 - 035x - 000 rev. 1.2 final
EM351 / em357 18 typical application figure 18 - 1 ill ustrates the typical application circuit , and table 18- 1 contains an example bill of materials (bo m) for the off - chip components required by the em35x . note: the circuit shown in figure 18- 1 is for example purposes only, and the bom is for budgetary quotes only. for a c omplete reference design, please download one of the latest silicon labs h ardware r eference d esigns from the silicon labs website ( www.silabs.com /zigbee - support ). the balun provides an impedance transformation from the antenna to the em35x for both t x and r x modes. l1 tunes the impedance presented to the rf port for maximum transmit power and receive sensitivity. the harmonic filter (l2 , l3 , c5 , c6 and c9 ) provides additional suppressio n of the second harmonic, which increases the margin over the fcc limit. the 24 mhz crystal y1 with loading capacitors is required and provides the high - frequency crystal oscillator source for the em35x ?s main system clock . the 32.768 khz crystal with loa ding capacitors generates a highly accurate low - frequency crystal oscillator for use with peripherals, but it is not mandatory as the low - frequency internal rc oscillator can be used. loading capacitance and esr (c1 and r3) provides stability for the inte rnal 1.8 v regulator. loading capacitance c2 provides stability for the internal 1.25 v regulator, no esr is required because it is contained within the chip. resistor r1 reduces the operating voltage of the flash memory, this reduces current consumption a nd improves sensitivity by 1 db when compared to not using it. various decoupling capacitors are required, these should be placed as close to their corresponding pins as possible. for values and locations see one of the latest reference designs. an antenna matched to 50 is required. 18- 1 120 - 035x - 000 rev. 1.2 final
EM351 / em357 figure 18 - 1 . typical application circuit dc vdd _ 24 mhz 1 vdd _ vco 2 rf _ p 3 rf _ n 4 vdd _ rf 5 rf _ tx _ alt _ p 6 rf _ tx _ alt _ n 7 vdd _ if 8 nc 9 vdd _ padsa 10 pc 5 11 nreset 12 pc 6 13 pc 7 14 vreg _ out 15 vdd _ pads 16 vdd _ core 17 pa 7 18 pb 3 19 pb 4 20 pa 0 21 pa 1 22 vdd _ pads 23 pa 2 24 osca 48 oscb 47 vdd _ synth 46 vdd _ pre 45 vdd _ core 44 pb 5 43 pb 6 42 pb 7 41 pc 0 40 vdd _ mem 39 pc 1 38 vdd _ pads 37 pb 0 36 pc 4 35 pc 3 34 pc 2 33 jtck 32 pb 2 31 pb 1 30 pa 6 29 vdd _ pads 28 pa 5 27 pa 4 26 pa 3 25 gnd 49 harmonic filter antenna ceramic balun em 35 x y 1 y 2 r 1 r 3 l 1 c 1 l 2 c 2 c 3 c 4 c 5 c 6 c 7 c 8 vbrd optional pc 2 pc 0 pc 3 jtck pc 4 nreset pa 4 pa 5 programing and debug interface ( these pins should be routed to test points ) l 3 c 9 18- 2 120 - 035x - 000 rev. 1.2 final
EM351 / em357 table 18 - 1 contains a typical bill of materials for the application circuit shown in figure 18 - 1 . the informatio n within this table should be used for a rough cost analysis. for a more detailed bom , please refer to one of silicon labs? em35x - based reference designs at the silicon labs website ( www.silabs.com /zigbee - support ) . tab le 18- 1 . bill of materials for figure 18 - 1 item qty reference description manufacturer 1 1 c2 capacitor, 1 f , 6.3 v, x5r, 10%, 0402 2 1 c1 capacitor, 2.2 f , 10 v, x5r, 10%, 0603 3 1 c7 capacitor, 22 pf , 5%, 50 v, npo, 0402 4 2 c3,c4 capacitor, 18 pf , 5%, 50 v, npo, 0402 5 1 c8 capacitor, 33 pf , 5%, 50 v, npo, 0402 6 2 c5, c 9 capacitor, 1 pf , 0.25 p f, 50 v, 0402, npo 7 1 c6 capacitor, 1.8pf, 0.25 pf, 50 v, 0402, npo 8 1 l1 inductor, 5.1 nh , 0.3 nh, 0402 multilayer murata lqg15hs5n1 9 2 l2 , l3 inductor, 2. 7 nh , 0.3 nh, 0402, multilayer murata lqg15hs2n7 10 1 r1 resistor, 10 , 5%, 0402 1 1 1 r3 resistor, 1 , 5%, 0402 1 2 1 u1 em35x single - chip zigbee/802.15.4 - 2003 solution ember em35x 1 3 1 y1 crystal, 24.000 mhz , 25 ppm stability over - 40 to +85 o c , 18 p f ilsi, abracon, kds, epson 1 4 1 y2 (optional) crystal, 32.768 khz , 20 ppm initial tolerance at +25 o c , 12. 5 pf abracon, kds , epson 1 5 1 bln1 balun, ceramic 50 / 200 wurth 748421245 johanson 2450bl15b100e murata ldb212g4010c 1 6 1 ant1 antenna johanson 2450at18b100e 18- 3 120 - 035x - 000 rev. 1.2 final
EM351 / em357 19 mechanical details the em35x package is a plastic 48 - pin qfn that is 7 mm x 7 mm x 0. 90 mm. figure 19 - 1 illu strates the package drawing. figure 19 - 1 . package drawing 19.1 qfn48 footprint recommendations figure 19 - 2 demonstrates the ipc - 7351 recommended pcb footprint for the em35x (qfn50p700x700x90 - 49n). a ground pad in the bottom center of the package forms a 49 th pin . a 3 x 3 array of non - the rmal vias should connect the em35x decal center shown in figure 19- 2 to the pcb ground plane through the ground pad. in order to properly solder the em35x to the footprint, the paste mask layer should have a 3 x 3 array of circular openings at 1.015 mm diameter spaced approximately 1.625 mm (center to center) apart, as shown in figure 19 - 3 . this will cause an evenly distributed solder flow and coplanar attachment to the pcb. the solder mask layer (illustrated in figure 19 - 4 ) should be the same as the copp er layer for the em35x footprint. for more information on the package footprint , please refer to the appropriate em35x reference design . top view edge view sym. minimum nominal maximum a common dimensions (mm) notes : 1 . jedec ref . mo - 220 2 . all dimensions are in millimeters 3 . pin 1 orientation identified by chamfer on corner of 4 . dimension e represents the terminal pitch detail b bottom view detail a detail b detail a pin 1 0.3000 a1 0 a2 d d2 e e1 5.5 e2 l b 0.225 0.25 0.275 e 0.50 r b min / 2 r 3 e e 1 e2 d1 d2 e l b a2 a1 exposed die pad 0.52 0.50 0.48 5.30 5.325 5.275 6.82 7.00 7.12 5.275 5.30 5.325 5.5 d1 6.82 7.00 7.12 0.20 0.05 0.90 1.00 0.80 a d 0.3000 exposed die pad 0.18 0.23 0.475 0.525 19- 1 120 - 035x - 000 rev. 1.2 final
EM351 / em357 figure 19 - 2 . pcb footprint for the em35x figure 19 - 3 . paste mask dimensions figure 19 - 4 . solder mask dimensions x2 y2 c1 e x1 y1 c2 min max typ x1 x2 y1 y2 c1 c2 e 6.85 6.85 0.30 5.35 0.90 5.35 0.50 * dimensions in mm * dimensions are for figures 19-2, 19-3 and 19-4 a1 b1 via drill dia = 0.254mm a0 b0 b0 b1 a0 a1 1.80 1.625 1.80 1.625 a2 a2 0.75 b2 0.75 b2 a1 c1 e x1 y1 c2 b1 b0 a0 dia = 1.01mm x2 y2 c1 e x1 y1 c2 a2 b2 19- 2 120 - 035x - 000 rev. 1.2 final
EM351 / em357 19.2 solder temperature profile figure 19 - 5 illustrates the solder temperature profile for the em35x . this temperature profile is similar for other rohs compliant packages, but manufacturing lines should be programmed with this profile in order to guarantee proper solder connection to the pcb. figure 19 - 5 . em35x reflow profile tsoak tsoak max tsoak min tpeak t peak t soak t 25c to t peak temperature time ramp-up 25c ramp-down t l table 19 - 1 contains the temperature p rofile parameters. table 19- 1 . solder reflow parameters parameter value average ramp up rate (from tsoak max to tpeak) 3 c per second max minimum soak temperature ( tsoak min ) 150 c maximum soak temperature (tsoak max ) 200 c tl 217 c time above tl 60 ? 150 seconds tpeak 260 + 0 c time within 5 c of tpeak 20 ? 40 seconds ramp down rate 6 c per second max time from 25 c to tpeak 8 minutes, max 19- 3 120 - 035x - 000 rev. 1.2 final
EM351 / em357 20 part marking figure 20 - 1 shows the part marking for the em300 series. the circ le in the top corner indicates p in 1. pins are numbered counter - clockwise from p in 1 with 12 pins per package edge. figure 20 - 1 . part marking for em35 x where: ? zzzzzz.zz defines the production lot code. ? yyww defines the year and week assembled. ? m defines the package assembly location (if there is no letter on the p ackage, then the package wa s as sembled in south wales) o w indicates south wales o c indicates china o m indicates malaysia zzzzzz . zz yyww m em 357 20- 1 120 - 035x - 000 rev. 1.2 final
EM351 / em357 21 ordering information use the following part numbers to order the em357: ? em357 - rtr ? reel contains 2000 units / reel ? em357 - rty ? sample tray use the following part numbers to order the EM351 : ? EM351 - rtr ? reel contains 2000 units / reel ? EM351 - rty ? sample tray the em300 series package is rohs - compliant. it conforms to the european court of justice decision regarding the deca - bde exemption of the rohs directive. it is pfos - compliant in acc ordance with european directive 2006/122/ec*1 released in december 2006. the em357 - rtr and EM351 - rtr reel conforms to eia specification 481. to order parts, contact silicon labs at 1+(877) 444 - 3032 , or find a sales office or distributor on our we b- site, www.silabs.com . 21- 1 120 - 035x - 000 rev. 1.2 final
EM351 / em357 22 shipping box label silicon labs includes the following information on each tape and reel box label (em357 - rtr or EM351 - rtr): ? package ? device type ? quantity (bar coded) ? box id (bar coded) ? lot number (bar coded) ? date code (bar coded) figure 22 - 1 depicts the label position on the box. as shown in this figure, there can be up to two date codes in a single tape and reel. figure 22 - 1 . contents label package 48 lead qfn device em 357 - rtr box qty 2000 box id xxxx - yyyyyy lot no aaaaaa . b . cc qty date yyww lot no dddddd . e . ff qty date yyww 22- 1 120 - 035x - 000 rev. 1.2 final
EM351 / em357 23 revision history revision location description of change 1.2 chapter 21 removed table 21 - 1 and figure 21 - 1. 1.1 table 2 - 3 update to table. m table 1 - 1, pin 48 update to table. section 6.1.2 and chapter 16 always - on domain power range change. chapter 9, tim1_or and tim2_or change tim 1 _extrigsel to tim_extrigsel . appendix c update to references. l datasheet rebranding to silicon labs . k chapter 1 chapter 5 section 7.5 adjusted naming and clarified description of fib monitor. chapter 20 added malaysia to package assembly locations. j section 9.3.5 register reference corrected. register tables tim_cc2s, timxccmr1, timx_ccmr2, timx_ccer minor corrections. i table 6 - 9, table 18 - 1 updates to tables. chapter 7 update to figure 7 - 2 and associated text. chapter 8 update to scx_spicfg register to clarify spi slave transmit padding. section 8.3.2 update 12 mhz spi master operation. h table 2 - 4 , table 6 - 9 updates to tables . section 8.4.1 and 8.4.3 new notes. chapter 21 update with rty information . g table 2 - 1 chapter 3 chapter 10 remove s references to high voltage mode . table 2 - 4 updates to table 2 - 4. section 6.4 better describes ember software capabilities. section 6.4.2 new note. section 8.6.2 adds information on conditions when uart can miss bytes. f figure 2 - 1 caption corrected, scaling updated. table 2 - 8 evm clarified. 23- 1 120 - 035x - 000 rev. 1.2 final
EM351 / em357 revision location description of change e table 1 - 1 pin 48 updated. table 2 - 7 updates to table 2 - 7 . chapter 2 changes to st comments and reset levels . table 6 - 8 supply dependence parameter now typical, not max. chapter 6 reset language clarified. section 10.5.3. new section. section 10.1.5 paragraph deleted. 10.4 calibration clarifications. 23- 2 120 - 035x - 000 rev. 1.2 final
EM351 / em357 appendix a register address table block cm_lv 40004000 - 40004038 cm_lv address name type reset description 40004038 peripheral_disable rw 0 peripheral disable register block interrupts 4000a000 - 4000afff interrupts address name type reset description 4000a800 int_tim1flag rw 0 timer 1 interrupt flag register 4000a804 int_tim2flag rw 0 timer 2 interrupt flag register 4000a808 int_sc1flag rw 0 serial controller 1 interrupt flag register 4000a80c int_sc2flag rw 0 serial controller 2 interrupt flag register 4000a810 int_adcflag rw 0 adc interrupt flag register 4000a814 int_gpioflag rw 0 gpio interrupt flag register 4000a818 int_tim1miss rw 0 timer 1 missed interrupt register 4000a81c int_tim2miss rw 0 timer 2 missed interrupts register 4000a820 int_miss rw 0 to p - level missed interrupts register 4000a840 int_tim1cfg rw 0 timer 1 interrupt configuration register 4000a844 int_tim2cfg rw 0 timer 2 interrupt configuration register 4000a848 int_sc1cfg rw 0 serial controller 1 interrupt configuration register 4000a84c int_sc2cfg rw 0 serial controller 2 interrupt configuration register 4000a850 int_adccfg rw 0 adc interrupt configuration register 4000a854 sc1_intmode rw 0 serial controller 1 interrupt mode register 4000a858 sc2_intmode rw 0 serial controller 2 interrupt mode register 4000a860 gpio_intcfga rw 0 gpio interrupt a configuration register 4000a864 gpio_intcfgb rw 0 gpio interrupt b configuration register 4000a868 gpio_intcfgc rw 0 gpio interrupt c configuration register 4000a86c gpio_intcfgd rw 0 gpio interrupt d configuration register a - 1 120 - 035x - 000 rev. 1.2 final
EM351 / em357 block gpio 4000b000 - 4000bfff general purpose io address name type reset description 4000b000 gpio_pacfgl rw 4444 port a configuration register (low) 4000b004 g p io _pac fgh rw 4444 port a configuration register (high) 4000b008 g p io _pai n rw 0 port a input data register 4000b00c gpio_paout rw 0 port a output data register 4000b010 g p io _pas e t rw 0 port a output set register 4000b014 g p io _pac l r rw 0 port a output clear register 4000b400 gpio_pbcfgl rw 4444 port b configuration register (low) 4000b404 gpio_pbcfgh rw 4444 port b configuration register (high) 4000b408 gpio_pbin rw 0 port b input data register 4000b40c gpio_pbout rw 0 port b output data register 4000b410 gpio_pbset rw 0 port b output set register 4000b414 gpio_pbclr rw 0 port b output clear register 4000b800 gpio_pccfgl rw 4444 port c configuration register (low) 4000b804 gpio_pccfgh rw 4444 port c configuration register (high) 4000b808 gpio_pcin rw 0 port c input data register 4000b80c gpio_pcout rw 0 port c output data register 4000b810 gpio_pcset rw 0 port c output set register 4000b814 gpio_pcclr rw 0 port c output clear register 4000bc00 gpio_dbgcfg rw 10 gpio debug configuration register 4000bc04 gpio_dbgstat r 0 gpio debug status register 4000bc08 g p io _pawak e rw 0 port a wakeup monitor register 4000bc0c gpio_pbwake rw 0 port b wakeup monitor register 4000bc10 gpio_pcwake rw 0 port c wakeup monitor register 4000bc14 gpio_irqcsel rw f interrupt c select register 4000bc18 gpio_irqdsel rw 10 interrupt d select register 4000bc1c g p io _wa k e fi lt rw 0 gpio wakeup filtering register a - 2 120 - 035x - 000 rev. 1.2 final
EM351 / em357 block serial 4000c000 - 4000cfff serial controllers address name type reset description 4000c000 sc2_rxbega rw 20000000 receive dma begin address register a 4000c004 sc2_rxenda rw 20000000 receive dma end address register a 4000c008 sc2_rxbegb rw 20000000 receive dma begin address register b 4000c00c sc2_rxendb rw 20000000 receive dma end address register b 4000c010 sc2_txbega rw 20000000 transmit dma begin address register a 4000c014 sc2_txenda rw 20000000 transmit dma end address register a 4000c018 sc2_txbegb rw 20000000 transmit dma begin address register b 4000c01c sc2_txendb rw 20000000 transmit dma end address register b 4000c020 sc2_rxcnta r 0 receive dma count register a 4000c024 sc2_rxcntb r 0 receive dma count register b 4000c028 sc2_txcnt r 0 transmit dma count register 4000c02c sc2_dmastat r 0 serial dma status register 4000c030 sc2_dmactrl rw 0 serial dma control register 4000c034 sc2_rxerra r 0 dma first receive error register a 4000c038 sc2_rxerrb r 0 dma first receive error register b 4000c03c sc2_data rw 0 serial data register 4000c040 sc2_spistat r 0 spi status register 4000c044 sc2_twistat r 0 twi status register 4000c04c sc2_twictrl1 rw 0 twi control register 1 4000c050 sc2_twictrl2 rw 0 twi control register 2 4000c054 sc2_mode rw 0 serial mode register 4000c058 sc2_spicfg rw 0 spi configuration register 4000c060 sc2_ratelin rw 0 serial clock linear prescaler register 4000c064 sc2_rateexp rw 0 serial clock exponential prescaler register 4000c070 sc2_rxcntsaved r 0 saved receive dma count register 4000c800 sc1_rxbega rw 20000000 receive dma begin address register a 4000c804 sc1_rxenda rw 20000000 receive dma end address register a 4000c808 sc1_rxbegb rw 20000000 receive dma begin address register b 4000c80c sc1_rxendb rw 20000000 receive dma end address register b 4000c810 sc1_txbega rw 20000000 transmit dma begin address register a 4000c814 sc1_txenda rw 20000000 transmit dma end address register a 4000c818 sc1_txbegb rw 20000000 transmit dma begin address register b 4000c81c sc1_txendb rw 20000000 transmit dma end address register b 4000c820 sc1_rxcnta r 0 receive dma count register a 4000c824 sc1_rxcntb r 0 receive dma count register b 4000c828 sc1_txcnt r 0 transmit dma count register 4000c82c sc1_dmastat r 0 serial dma status register 4000c830 sc1_dmactrl rw 0 serial dma control register a - 3 120 - 035x - 000 rev. 1.2 final
EM351 / em357 block serial 4000c000 - 4000cfff serial controllers address name type reset description 4000c834 sc1_rxerra r 0 dma first receive error register a 4000c838 sc1_rxerrb r 0 dma first receive error register b 4000c83c sc1_data rw 0 serial data register 4000c840 sc1_spistat r 0 spi status register 4000c844 sc1_twistat r 0 twi status register 4000c848 sc1_uartstat r 40 uart status register 4000c84c sc1_twictrl1 rw 0 twi control register 1 4000c850 sc1_twictrl2 rw 0 twi control register 2 4000c854 sc1_mode rw 0 serial mode register 4000c858 sc1_spicfg rw 0 spi configuration register 4000c85c sc1_uartcfg rw 0 uart configuration register 4000c860 sc1_ratelin rw 0 serial clock linear prescaler register 4000c864 sc1_rateexp rw 0 serial clock exponential prescaler register 4000c868 sc1_uartper rw 0 uart baud rate period register 4000c86c sc1_uartfrac rw 0 uart baud rate fractional period register 4000c870 sc1_rxcntsaved r 0 saved receive dma count register block adc 4000d000 - 4000dfff analog to digital converter address name type reset description 4000d000 adc_data r 0 adc data register 4000d004 adc_cfg rw 00001800 adc configuration register 4000d008 adc_offset rw 0000 adc offset register 4000d00c adc_gain rw 8000 adc gain register 4000d010 adc_dmacfg rw 0 adc dma configuration register 4000d014 adc_dmastat r 0 adc dma status register 4000d018 adc_dmabeg rw 20000000 adc dma begin address register 4000d01c adc_dmasize rw 0 adc dma buffer size register 4000d020 adc_dmacur r 20000000 adc dma current address register 4000d024 adc_dmacnt r 0 adc dma count register a - 4 120 - 035x - 000 rev. 1.2 final
EM351 / em357 block tim1 4000e000 - 4000efff general purpose timer 1 address name type reset description 4000e000 tim1_cr1 rw 0 timer 1 control register 1 4000e004 tim1_cr2 rw 0 timer 1 control register 2 4000e008 tim1_smcr rw 0 timer 1 slave mode control register 4000e014 tim1_egr rw 0 timer 1 event generation register 4000e018 tim1_ccmr1 rw 0 timer 1 capture/compare mode register 1 4000e01c tim1_ccmr2 rw 0 timer 1 capture/compare mode register 2 4000e020 tim1_ccer rw 0 timer 1 capture/compare enable register 4000e024 tim1_cnt rw 0 timer 1 counter register 4000e028 tim1_psc rw 0 timer 1 prescaler register 4000e02c tim1_arr rw ffff timer 1 auto - reload register 4000e034 tim1_ccr1 rw 0 timer 1 capture/compare register 1 4000e038 tim1_ccr2 rw 0 timer 1 capture/compare register 2 4000e03c tim1_ccr3 rw 0 timer 1 capture/compare register 3 4000e040 tim1_ccr4 rw 0 timer 1 capture/compare register 4 4000e050 tim1_or rw 0 timer 1 option register block tim2 4000f000 - 4000ffff general purpose timer 2 address name type reset description 4000f000 tim2_cr1 rw 0 timer 2 control register 1 4000f004 tim2_cr2 rw 0 timer 2 control register 2 4000f008 tim2_smcr rw 0 timer 2 slave mode control register 4000f014 tim2_egr rw 0 timer 2 event generation register 4000f018 tim2_ccmr1 rw 0 timer 2 capture/compare mode register 1 4000f01c tim2_ccmr2 rw 0 timer 2 capture/compare mode register 2 4000f020 tim2_ccer rw 0 timer 2 capture/compare enable register 4000f024 tim2_cnt rw 0 timer 2 counter register 4000f028 tim2_psc rw 0 timer 2 prescaler register 4000f02c tim2_arr rw ffff timer 2 auto - reload register 4000f034 tim2_ccr1 rw 0 timer 2 capture/compare register 1 4000f038 tim2_ccr2 rw 0 timer 2 capture/compare register 2 4000f03c tim2_ccr3 rw 0 timer 2 capture/compare register 3 4000f040 tim2_ccr4 rw 0 timer 2 capture/compare register 4 4000f050 tim2_or rw 0 timer 2 option register a - 5 120 - 035x - 000 rev. 1.2 final
EM351 / em357 block nvic e000e000 - e000efff nested vectored interrupt controller address name type reset description e000e100 int_cfgset rw 0 to p - level set interrupts configuration register e000e180 int_cfgclr rw 0 to p - level clear interrupts configuration register e000e200 int_pendset rw 0 to p - level set interrupts pending register e000e280 int_pendclr rw 0 to p - level clear interrupts pending register e000e300 int_active r 0 to p - level active interrupts register e000ed3c scs_afsr rw 0 auxiliary fault status register a - 6 120 - 035x - 000 rev. 1.2 final
EM351 / em357 appendix b abbreviations and acronyms acronym/abbreviation meaning ack acknowledgement adc analog to digital converter aes advanced encryption standard agc automatic gain control ahb advanced high speed bus apb advanced peripheral bus cbc - mac cipher block chaining ? message authentication code cca clear channel assessment ccm counter with cbc - mac mode for aes encryption ccm* improved counter with cbc - mac mode for aes encryption cib customer information block clk1k 1 khz clock clk32k 32.768 khz crystal clock cpu central processing unit crc cyclic redundancy check csma - ca carrier sense multiple access - collision avoidance ctr counter mode cts clear to send dnl differential non - linearity dma direct memory access dwt data watchpoint and trace eeprom electrically erasable programmable read only memory em event manager enob effective number of bits esd electro static discharge esr equivalent series resistance etr external trigger input fclk arm ? cortex tm - m3 cpu clock fib fixed information block fifo first - in, first - out b - 1 120 - 035x - 000 rev. 1.2 final
EM351 / em357 acronym/abbreviation meaning fpb flash patch and breakpoint gpio general purpose i/o (pins) hf high frequency i 2 c inter - integrated circuit ide integrated development environment if intermediate frequency ieee institute of electrical and electronics engineers inl integral non - linearity itm instrumentation trace macrocell jtag joint test action group lf low frequency lna low noise amplifier lqi link quality indicator lsb least significant bit mac medium access control mfb main flash block miso master in, slave out mos metal oxide semiconductor (p - channel or n - channel) mosi master out, slave in mpu memory protection unit msb most significant bit msl moisture sensitivity level nack negative acknowledge nist national institute of standards and technology nmi non - maskable interrupt nvic nested vectored interrupt controller opm one - pulse mode o - qpsk offset - quadrature phase shift keying osc24m high frequency crystal oscillator osc32k low - frequency 32.768 khz oscillator oschf high - frequency internal rc oscillator b - 2 120 - 035x - 000 rev. 1.2 final
EM351 / em357 acronym/abbreviation meaning oscrc low - frequency rc oscillator pa power amplifier pclk peripheral clock per packet error rate phy physical layer pll phase - locked loop por power - on - reset prng pseudo random number generator psd power spectral density pti packet trace interface pwm pulse width modulation qfn quad flat pack ram random access memory rc resistive/capacitive rf radio frequency rms root mean square rohs restriction of hazardous substances rssi receive signal strength indicator rts request to send rx receive s ys clk system clock sdfr spurious free dynamic range sfd start frame delimiter sinad signal - to - noise and distortion ratio spi serial peripheral interface swj serial wire and jtag interface thd total harmonic distortion trng true random number generator twi two wire serial interface tx transmit uart universal asynchronous receiver/transmitter b - 3 120 - 035x - 000 rev. 1.2 final
EM351 / em357 acronym/abbreviation meaning uev update event vco voltage controlled oscillator abbreviation meaning db decibel dbc decibels relative to the carrier dbm decibels relative to 1 mw ghz gigaherz kb kilobyte kbps kilobits/second khz kiloherz k kiloohm kv kilovolt ma milliampere mbps megabits per second mhz megaherz m megaohm msps megasamples per second a microampere sec microsecond nh nanohenry ns nanoseconds ohm pf picofarad ppm part per million v volt b - 4 120 - 035x - 000 rev. 1.2 final
EM351 / em357 appendix c references ? zigbee specification ( www.zigbee.org ; zigbee document 053474 ) (zigbee alliance membership required) ? zigbee - pro stack profile ( www.zigbee.org ; zigbee document 074855) (zigbee alliance membership required) ? zigbee stack profile ( www.zigbee.org ; zigbee document 064321) (zigbee alliance membership required) ? blue tooth core specification v2.1 ( http://www.bluetooth.org/docman/handlers/downloaddoc.ashx?doc_id=241363 ) ? ieee 802.15.4 - 2003 ( http://standards.ieee.org/getieee802/download/802.15.4 - 2003.pdf ) ? ieee 802.11g ( standards.ieee.org/getieee802/download/802.11g - 2003.pdf ) ? arm ? cortex ? - m3 reference manual ( http://infocenter.arm.com/help/topic/com.arm.doc.subset.cortexm.m3/index.html#cortexm3 ) copyright ? 2012 silicon laboratories the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissi ons, and disclaims responsibility for any consequences resulting from the use of information included herein. additionally, silicon laboratories assumes no responsibility for the functioning of undescribed features or parameters. silicon laboratories reser ves the right to make changes without further notice. silicon laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories assume any liability arising out o f the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. silicon laboratories products are not designed, intended, or authorized for use in appli cations intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a situation where personal injury or death may occur. should buyer purchase or use silicon laboratories products for any such unintended or unauthorized application, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. silicon laboratories, silicon labs, and ember are registered trademarks of silicon laboratories inc. other p roducts or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. c -1 120 - 035x - 000 rev. 1.2 final

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